Selective triple modular redundancy (STMR) based single-event upset (SEU) tolerant synthesis for FPGAs

IEEE Transactions on Nuclear Science

Volumn 51, Issue 5 IV, 2004, Pages 2957-2969

  Samudrala, Praveen Kumar ^a   Ramos, Jeremy ^b   Katkoori, Srinivas ^c  

^a MicroConstants Inc   (United States)

^b Honeywell Space Systems Clearwater   (United States)

^c UNIVERSITY OF SOUTH FLORIDA   (United States)

Author keywords

Field programmable gate array (FPGA); Single event upset (SEU); Triple modular redundancy (TMR)

Indexed keywords

ALGORITHMS; DIGITAL CIRCUITS; MAJORITY LOGIC; REDUNDANCY; SEQUENTIAL CIRCUITS; STATIC RANDOM ACCESS STORAGE; TABLE LOOKUP;

SENSITIVE SUBCIRCUITS; SINGLE EVENT UPSET (SEU); TRIPLE MODULAR REDUNDANCY (TMR); VOTER CIRCUITS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 8344278950     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2004.834955     Document Type: Article

References (28)

1. SEU mitigation techniques for Virtex FPGA's in space applications, P. Blain, C. Carmichael, E. Fuller, and M. Caffrey. [Online]. Available: http://www.xilinx.com/appnotes/VtxSEU.pdf
2. Q. Shi and G. K. Maki, "New design techniques for SEU immune circuits," in 9th NASA Symp. VLSI Design, 2000, pp. 4.2.1-4.2.16.
3. MCNC 91 Benchmarks [Online]. Available: http://www.cbl.ncsu.edu
4. E. M. Sentovich et al., SIS: A system for sequential circuit synthesis, May 1992.
5. K. A. Label and M. M. Gates, "Single-event-effect mitigation from a system perspective," IEEE Trans. Nucl. Sci., vol. 43, no. 2, 1996.
6. C. Carmichael, Triple modular redundancy design techniques for Virtex FPGA's (DRAFT), 2001.
7. P. Brinkley, P. Avnet, and C. Carmichael, SEU mitigation design techniques for the XQR4000XL, 2000.
8. S. Whitaker, "Single event upset hardening CMOS memory circuit," U.S. Patent no. 5111429.
9. J. Canaris, S. Whitaker, and M. N. Liu, "SEU hardened memory cells for a CCSDS Reed Solomon encoder," IEEE Trans. Nucl. Sci., vol. 38, pp. 1471-1477, Dec. 1991.
10. M. N. Liu and S. Whitaker, "Low power SEU immune CMOS memory circuits," IEEE Trans. Nucl. Sci., vol. 39, pp. 1679-1684, Dec. 1992.
11. M. Nicolaidis, T. Calin, and R. Velazco, "Upset hardened memory design for submicron CMOS technology," IEEE Trans. Nucl. Sci., vol. 43, pp. 2874-2878, Dec. 1996.
12. N. Kumar, S. Katkoori, L. Rader, and R. Vemuri, "Profile-driven behavioral synthesis for low power VLSI systems," IEEE Design Test Comput., pp. 70-84, 1995.
13. C. Tsui, R. Marculescu, D. Marculescu, and M. Pedram, "Improving the efficiency of power simulators by input vector compaction," in Design Automation Conf. Proc., June 1996, pp. 165-168.
14. R. Marculescu, D. Marculescu, and M. Pedram, "Vector compaction using dynamic Markov models," IEICE Trans. Fundamentals (Special Issue on VLSI design and CAD Algorithms), Oct. 1997.
15. R. Velazco and D. Bessot et al., "Two CMOS memory cells suitable for the design of SEU-tolerant VLSI circuits," IEEE Trans. Nucl. Sci., vol. 41, pp. 2229-2234, 1994.
16. M. J. Barry, "Radiation resistant SRAM memory cell," U.S. Patent no. 5157625.
17. J. G. Dooley, "SEU-immune for gate array, standard cell, and other ASIC applications," U.S. Patent no. 5 311070.
18. F. Vargas and M. Nicolaidis, "SEU-tolerant SRAM design based on current monitoring," in 24th Int. Symp. Fault Tolerant Computing, June 1994, pp. 106-115.
19. M. Nicolaidis, T. Calin, F. Vargas, and R. Velazco, "A low-cost, highly reliable SEU-tolerant SRAM: prototype and test results," IEEE Trans. Nucl. Sci., vol. 42, pp. 1592-1598, 1995.
20. L. R. Rockett Jr., "Simulated SEU hardened scaled CMOS SRAM cell design using gated resistors," IEEE Trans. Nucl. Sci., vol. 39, no. 5, pp. 1532-1541, Oct. 1992.
21. J. Canaris and S. Whitaker, "Circuit techniques for the radiation environment of the space," in IEEE 1995 Custom Integrated Circuits Conf., 1995, pp. 5.4.1-5.4.4.
22. J. Venbrux, K. Cameron, K. Arave, L. Arave, M. N. Liu, D. Wiseman, J. Canaris, and K. Liu, "Design and testing of SEU/SEL immune memory and logic circuits in a commercial CMOS process," in Rec. 1993 IEEE Radiation Effects Data Workshop, July 1993, pp. 51-55.
23. K. C. Holland and J. G. Tront, "Probability of latching single event upset errors in VLSI circuits," in IEEE Proc. Southeastcon '91, Apr. 1991, pp. 109-113.
24. J. Von Neumann, "Probabilistic logics and synthesis of reliable organizms from unreliable components," in Automata Studies, C. E. Shannon and J. McCarthy, Eds. Princeton, NJ: Princeton Univ. Press, 1956, pp. 43-98.
25. K. J. Hass, "Probabilistic estimates of upset caused by single event transients," in 8th NASA Symp. VLSI Design, 1999, pp. 4.3.1-4.3.9.
26. G. S. Ditlow, J. Savir, and P. H. Bardell, "Radom pattern testability," IEEE Trans. Computers, vol. C-33, pp. 79-90, Jan. 1984.
27. M. A. Breuer, M. Abramvoici, and A. D. Friedman, Digital Systems Testing and Testable Design: IEEE, 1990.
28. D. G. Mavis and P. H. Eaton, "SEU and SET mitigation techniques for FPGA circuit and configuration bit storage design," in Proc. 2000 Military and Aerospace Applications of Programmable Devices and Technol. Conf., Sept. 2000.