Test-pattern grading and pattern selection for small-delay defects

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2008, Pages 233-239

  Yilmaz, Mahmut ^a   Chakrabarty, Krishnendu ^a   Tehranipoor, Mohammad ^b  

^a Duke University

^b UNIVERSITY OF CONNECTICUT   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY DEFECTS; NANOMETER TECHNOLOGIES; VLSI TESTS;

COMPUTATIONAL COMPLEXITY; COMPUTER NETWORKS; DEFECTS; METAL DETECTORS; POWER QUALITY; PROCESS ENGINEERING; RISK ASSESSMENT; TIME DELAY; TIME MEASUREMENT;

AUTOMATIC TEST PATTERN GENERATION;

EID: 51449106946     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2008.32     Document Type: Conference Paper

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