-
1
-
-
4544316746
-
A novel sub-50 nm multi-bridge-channel MOSFET (MBCFET) with extremely high performance
-
S. Y. Lee, E. J. Yoon, S. M. Kim, C. W. Oh, M. Li, J. D. Choi, K. H. Yeo, M. S. Kim, H. J. Cho, S. H. Kim, D. W. Kim, D. Park, and K. Kim, "A novel sub-50 nm multi-bridge-channel MOSFET (MBCFET) with extremely high performance," in VLSI Symp. Tech. Dig., 2004, pp. 200-201.
-
(2004)
VLSI Symp. Tech. Dig
, pp. 200-201
-
-
Lee, S.Y.1
Yoon, E.J.2
Kim, S.M.3
Oh, C.W.4
Li, M.5
Choi, J.D.6
Yeo, K.H.7
Kim, M.S.8
Cho, H.J.9
Kim, S.H.10
Kim, D.W.11
Park, D.12
Kim, K.13
-
2
-
-
33745170382
-
Sub-25 nm single-metal gate multi-bridge-channel MOSFET (MBCFET) for high performance and low power application
-
S. Y. Lee, E. J. Yoon, D. S. Shin, S. M. Kim, S. D. Suk, M. S. Kim, D.W. Kim, D. Park, K. Kim, and B. I. Ryu, "Sub-25 nm single-metal gate multi-bridge-channel MOSFET (MBCFET) for high performance and low power application," in VLSI Symp. Tech. Dig., 2005, pp. 154-155.
-
(2005)
VLSI Symp. Tech. Dig
, pp. 154-155
-
-
Lee, S.Y.1
Yoon, E.J.2
Shin, D.S.3
Kim, S.M.4
Suk, S.D.5
Kim, M.S.6
Kim, D.W.7
Park, D.8
Kim, K.9
Ryu, B.I.10
-
3
-
-
37749045191
-
122 Mb high speed SRAM cell with 25 nm gate length multi-bridge-channel MOSFET (MBCFET) on bulk Si substrate
-
M. S. Kim, S. Y. Lee, E. J. Yoon, S. M. Kim, J. Lian, K. H. Lee, N. M. Cho, M. S. Lee, D. Hwang, Y. S. Lee, D. W. Kim, D. Park, K. Kim, and B. I. Ryu, "122 Mb high speed SRAM cell with 25 nm gate length multi-bridge-channel MOSFET (MBCFET) on bulk Si substrate," in VLSI Symp. Tech. Dig., 2006, pp. 68-69.
-
(2006)
VLSI Symp. Tech. Dig
, pp. 68-69
-
-
Kim, M.S.1
Lee, S.Y.2
Yoon, E.J.3
Kim, S.M.4
Lian, J.5
Lee, K.H.6
Cho, N.M.7
Lee, M.S.8
Hwang, D.9
Lee, Y.S.10
Kim, D.W.11
Park, D.12
Kim, K.13
Ryu, B.I.14
-
4
-
-
59649114951
-
2 gate stack
-
Feb
-
2 gate stack," IEEE Electron Device Lett., vol. 30, no. 2, pp. 148-151, Feb. 2009.
-
(2009)
IEEE Electron Device Lett
, vol.30
, Issue.2
, pp. 148-151
-
-
Bernard, E.1
Ernst, T.2
Guillaumot, B.3
Vulliet, N.4
Lim, T.C.5
Rozeau, O.6
Danneville, F.7
Skotnicki, T.8
Deleonibus, S.9
Faynot, O.10
-
5
-
-
85008006353
-
Vertically stacked SiGe nanowire array channel CMOS transistors
-
Mar
-
W. W. Fang, N. Singh, L. K. Bera, H. S. Nguyen, S. C. Rustagi, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, "Vertically stacked SiGe nanowire array channel CMOS transistors," IEEE Electron Device Lett., vol. 28, no. 3, pp. 211-213, Mar. 2007.
-
(2007)
IEEE Electron Device Lett
, vol.28
, Issue.3
, pp. 211-213
-
-
Fang, W.W.1
Singh, N.2
Bera, L.K.3
Nguyen, H.S.4
Rustagi, S.C.5
Lo, G.Q.6
Balasubramanian, N.7
Kwong, D.-L.8
-
6
-
-
46049086980
-
-
2/TiN gate stack, in IEDM Tech. Dig., 2006, pp. 997-1000.
-
2/TiN gate stack," in IEDM Tech. Dig., 2006, pp. 997-1000.
-
-
-
-
7
-
-
64549147010
-
15 nm-diameter 3D stacked nanowires with independent gates operation: ΦFET
-
C. Dupré, A. Hubert, S. Becu, M. Jublot, V. Maffini-Alvaro, C. Vizioz, F. Aussenac, C. Arvet, S. Barnola, J.-M. Hartmann, G. Garnier, F. Allain, J.-P. Colonna, M. Rivoire, L. Baud, S. Pauliac, V. Loup, P. Rivallin, B. Guillaumot, G. Ghibaudo, O. Faynot, T. Ernst, and S. Deleonibus, "15 nm-diameter 3D stacked nanowires with independent gates operation: ΦFET," in IEDM Tech. Dig., 2008, pp. 749-752.
-
(2008)
IEDM Tech. Dig
, pp. 749-752
-
-
Dupré, C.1
Hubert, A.2
Becu, S.3
Jublot, M.4
Maffini-Alvaro, V.5
Vizioz, C.6
Aussenac, F.7
Arvet, C.8
Barnola, S.9
Hartmann, J.-M.10
Garnier, G.11
Allain, F.12
Colonna, J.-P.13
Rivoire, M.14
Baud, L.15
Pauliac, S.16
Loup, V.17
Rivallin, P.18
Guillaumot, B.19
Ghibaudo, G.20
Faynot, O.21
Ernst, T.22
Deleonibus, S.23
more..
-
8
-
-
0033280988
-
SON (Silicon on Nothing) - A new device architecture for the VLSI era
-
M. Jurczak, T. Skotnicki, M. Paoli, B. Tormen, J.-L. Regolini, C. Morin, A. Schiltz, J. Martins, R. Pantel, and J. Galvier, "SON (Silicon on Nothing) - A new device architecture for the VLSI era," in VLSI Symp. Tech. Dig., 1999, pp. 29-30.
-
(1999)
VLSI Symp. Tech. Dig
, pp. 29-30
-
-
Jurczak, M.1
Skotnicki, T.2
Paoli, M.3
Tormen, B.4
Regolini, J.-L.5
Morin, C.6
Schiltz, A.7
Martins, J.8
Pantel, R.9
Galvier, J.10
-
9
-
-
0035717576
-
First 80 nm SON (Silicon-on-Nothing) MOSFETs with perfect morphology and high electrical performance
-
S. Monfray, T. Skotnicki, Y. Morand, S. Descombes, M. Paoli, P. Ribot, A. Talbot, D. Dutartre, F. Leverd, Y. Lefriec, R. Pantel, M. Haond, D. Renaud, M.-E. Nier, C. Vizioz, and D. Louis, "First 80 nm SON (Silicon-on-Nothing) MOSFETs with perfect morphology and high electrical performance," in IEDM Tech. Dig., 2001, pp. 645-648.
-
(2001)
IEDM Tech. Dig
, pp. 645-648
-
-
Monfray, S.1
Skotnicki, T.2
Morand, Y.3
Descombes, S.4
Paoli, M.5
Ribot, P.6
Talbot, A.7
Dutartre, D.8
Leverd, F.9
Lefriec, Y.10
Pantel, R.11
Haond, M.12
Renaud, D.13
Nier, M.-E.14
Vizioz, C.15
Louis, D.16
-
10
-
-
0036045162
-
50 nm-Gate All Around (GAA)-Silicon on Nothing (SON)-devices: A simple way to co-integration of GAA transistors within bulk MOSFET process
-
S. Monfray, T. Skotnicki, Y. Morand, S. Descombes, P. Coronel, P. Mazoyer, S. Harrison, P. Ribot, A. Talbot, D. Dutartre, M. Haond, R. Palla, Y. Lefriec, F. Leverd, M.-E. Nier, C. Vizioz, and D. Louis, "50 nm-Gate All Around (GAA)-Silicon on Nothing (SON)-devices: A simple way to co-integration of GAA transistors within bulk MOSFET process," in VLSI Symp. Tech. Dig., 2002, pp. 108-109.
-
(2002)
VLSI Symp. Tech. Dig
, pp. 108-109
-
-
Monfray, S.1
Skotnicki, T.2
Morand, Y.3
Descombes, S.4
Coronel, P.5
Mazoyer, P.6
Harrison, S.7
Ribot, P.8
Talbot, A.9
Dutartre, D.10
Haond, M.11
Palla, R.12
Lefriec, Y.13
Leverd, F.14
Nier, M.-E.15
Vizioz, C.16
Louis, D.17
-
11
-
-
17644439016
-
Highly performant double-gate MOSFET realized with SON process
-
S. Harrison, P. Coronel, F. Leverd, R. Cerutti, R. Palla, D. Delille, S. Borel, S. Jullian, R. Pantel, S. Descombes, D. Dutartre, Y. Morand, M.-P. Samson, D. Lenoble, A. Talbot, A. Villaret, S. Monfray, P. Mazoyer, J. Bustos, H. Brut, A. Cros, D. Munteanu, J.-L. Autran, and T. Skotnicki, "Highly performant double-gate MOSFET realized with SON process," in IEDM Tech. Dig., 2003, pp. 449-452.
-
(2003)
IEDM Tech. Dig
, pp. 449-452
-
-
Harrison, S.1
Coronel, P.2
Leverd, F.3
Cerutti, R.4
Palla, R.5
Delille, D.6
Borel, S.7
Jullian, S.8
Pantel, R.9
Descombes, S.10
Dutartre, D.11
Morand, Y.12
Samson, M.-P.13
Lenoble, D.14
Talbot, A.15
Villaret, A.16
Monfray, S.17
Mazoyer, P.18
Bustos, J.19
Brut, H.20
Cros, A.21
Munteanu, D.22
Autran, J.-L.23
Skotnicki, T.24
more..
-
12
-
-
66949114030
-
-
A. Pouydebasque, S. Denorme, P. Coronel, N. Loubet, R. Wacquez, J. Bustos, F. Leverd, P. Gouraud, J.-D. Chapon, M. Dartora, X. Gérard, G. Chabanne, T. Kormann, M. Grosjean, E. Deloffre, N. Emonet, P. Morin, A. Zauner, S. Barnola, M. Aminpur, C. Laviron, S. Gaillard, D. Fleury, A. Cros, D. Delille, D. Dutartre, F. Boeuf, and T. Skotnicki, High performance high-K/metal planar self-aligned Gate-All-Around CMOS devices for 32 nm technologies and beyond, in Proc. Silicon Nano-Workshop, 2007, pp. 3-4.
-
A. Pouydebasque, S. Denorme, P. Coronel, N. Loubet, R. Wacquez, J. Bustos, F. Leverd, P. Gouraud, J.-D. Chapon, M. Dartora, X. Gérard, G. Chabanne, T. Kormann, M. Grosjean, E. Deloffre, N. Emonet, P. Morin, A. Zauner, S. Barnola, M. Aminpur, C. Laviron, S. Gaillard, D. Fleury, A. Cros, D. Delille, D. Dutartre, F. Boeuf, and T. Skotnicki, "High performance high-K/metal planar self-aligned Gate-All-Around CMOS devices for 32 nm technologies and beyond," in Proc. Silicon Nano-Workshop, 2007, pp. 3-4.
-
-
-
-
13
-
-
0028496958
-
x layers on Si
-
Sep
-
x layers on Si," J. Cryst. Growth, vol. 142, no. 1/2, pp. 78-86, Sep. 1994.
-
(1994)
J. Cryst. Growth
, vol.142
, Issue.1-2
, pp. 78-86
-
-
Dutartre, D.1
Warren, P.2
Chollet, F.3
Gisbert, F.4
Bérenguer, M.5
Berbèzier, I.6
-
14
-
-
0003081256
-
Evolution of surface morphology and strain during SiGe epitaxy
-
Dec
-
A. J. Pidduck, D. J. Robbins, A. G. Cullis, W. Y. Leong, and A. M. Pitt, "Evolution of surface morphology and strain during SiGe epitaxy," Thin Solid Films, vol. 222, no. 1/2, pp. 78-84, Dec. 1992.
-
(1992)
Thin Solid Films
, vol.222
, Issue.1-2
, pp. 78-84
-
-
Pidduck, A.J.1
Robbins, D.J.2
Cullis, A.G.3
Leong, W.Y.4
Pitt, A.M.5
-
15
-
-
24144500757
-
Growth of SiGe/Si superlattices on silicon-on-insulator substrates for multi-bridge channel field effect transistors
-
Sep
-
J. M. Hartmann, P. Holliger, F. Laugier, G. Rolland, A. Suhm, T. Ernst, T. Billon, and N. Vulliet, "Growth of SiGe/Si superlattices on silicon-on-insulator substrates for multi-bridge channel field effect transistors," J. Cryst. Growth, vol. 283, no. 1/2, pp. 57-67, Sep. 2005.
-
(2005)
J. Cryst. Growth
, vol.283
, Issue.1-2
, pp. 57-67
-
-
Hartmann, J.M.1
Holliger, P.2
Laugier, F.3
Rolland, G.4
Suhm, A.5
Ernst, T.6
Billon, T.7
Vulliet, N.8
-
16
-
-
51949096074
-
Novel integration process and performance analysis of Low STandby Power (LSTP) 3D Multi-Channel CMOSFET (MCFET) on SOI with metal/high-K gate stack
-
E. Bernard, T. Ernst, B. Guillaumot, N. Vulliet, V. Barral, V. Maffini-Alvaro, F. Andrieu, C. Vizioz, Y. Campidelli, P. Gautier, J. M. Hartmann, R. Kies, V. Delaye, F. Aussenac, T. Poiroux, P. Coronel, A. Souifi, T. Skotnicki, and S. Deleonibus, "Novel integration process and performance analysis of Low STandby Power (LSTP) 3D Multi-Channel CMOSFET (MCFET) on SOI with metal/high-K gate stack," in VLSI Symp. Tech. Dig., 2008, pp. 16-17.
-
(2008)
VLSI Symp. Tech. Dig
, pp. 16-17
-
-
Bernard, E.1
Ernst, T.2
Guillaumot, B.3
Vulliet, N.4
Barral, V.5
Maffini-Alvaro, V.6
Andrieu, F.7
Vizioz, C.8
Campidelli, Y.9
Gautier, P.10
Hartmann, J.M.11
Kies, R.12
Delaye, V.13
Aussenac, F.14
Poiroux, T.15
Coronel, P.16
Souifi, A.17
Skotnicki, T.18
Deleonibus, S.19
-
17
-
-
66949139758
-
Multichannel Field-Effect Transistors (MCFET) - Part II: Analysis of gate stack and series resistance influence on the MCFET performance
-
Jun
-
E. Bernard, T. Ernst, B. Guillaumot, N. Vulliet, X. Garros, P. Coronel, T. Skotnicki, S. Deleonibus, and O. Faynot, "Multichannel Field-Effect Transistors (MCFET) - Part II: Analysis of gate stack and series resistance influence on the MCFET performance," IEEE Trans. Electron Devices, vol. 56, no. 6, pp. 1252-1261, Jun. 2009.
-
(2009)
IEEE Trans. Electron Devices
, vol.56
, Issue.6
, pp. 1252-1261
-
-
Bernard, E.1
Ernst, T.2
Guillaumot, B.3
Vulliet, N.4
Garros, X.5
Coronel, P.6
Skotnicki, T.7
Deleonibus, S.8
Faynot, O.9
-
18
-
-
17344374600
-
Isotropic etching of SiGe alloys with high selectivity to similar materials
-
Jun
-
S. Borel, C. Arvet, J. Bilde, S. Harrison, and D. Louis, "Isotropic etching of SiGe alloys with high selectivity to similar materials," Microelectron. Eng., vol. 73/74, pp. 301-305, Jun. 2004.
-
(2004)
Microelectron. Eng
, vol.73-74
, pp. 301-305
-
-
Borel, S.1
Arvet, C.2
Bilde, J.3
Harrison, S.4
Louis, D.5
-
19
-
-
0036932011
-
75 nm damascene metal gate and high-k integration for advanced CMOS devices
-
B. Guillaumot, X. Garros, F. Lime, K. Oshima, B. Tavel, J. A. Chroboczek, P. Masson, R. Truche, A. M. Papon, F. Martin, J. F. Damlencourt, S. Maitrejean, M. Rivoire, C. Leroux, S. Cristoloveanu, G. Ghibaudo, J. L. Autran, T. Skotnicki, and S. Deleonibus, "75 nm damascene metal gate and high-k integration for advanced CMOS devices," in IEDM Tech. Dig., 2002, pp. 355-358.
-
(2002)
IEDM Tech. Dig
, pp. 355-358
-
-
Guillaumot, B.1
Garros, X.2
Lime, F.3
Oshima, K.4
Tavel, B.5
Chroboczek, J.A.6
Masson, P.7
Truche, R.8
Papon, A.M.9
Martin, F.10
Damlencourt, J.F.11
Maitrejean, S.12
Rivoire, M.13
Leroux, C.14
Cristoloveanu, S.15
Ghibaudo, G.16
Autran, J.L.17
Skotnicki, T.18
Deleonibus, S.19
-
20
-
-
46049113111
-
-
2 as a metal gate stack for FDSOI cMOSFETs down to 25 nm gate length and width, in IEDM Tech. Dig., 2006, pp. 641-644.
-
2 as a metal gate stack for FDSOI cMOSFETs down to 25 nm gate length and width," in IEDM Tech. Dig., 2006, pp. 641-644.
-
-
-
-
21
-
-
0031078092
-
A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation
-
Feb
-
Y. Cheng, M. C. Jeng, Z. Liu, J. Huang, M. Chan, K. Chen, P. K. Ko, and C. Hu, "A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation," IEEE Trans. Electron Devices, vol. 44, no. 2, pp. 277-287, Feb. 1997.
-
(1997)
IEEE Trans. Electron Devices
, vol.44
, Issue.2
, pp. 277-287
-
-
Cheng, Y.1
Jeng, M.C.2
Liu, Z.3
Huang, J.4
Chan, M.5
Chen, K.6
Ko, P.K.7
Hu, C.8
-
22
-
-
40849143850
-
3D stacked channels: How series resistances can limit 3D devices performance
-
E. Bernard, T. Ernst, B. Guillaumot, N. Vulliet, V. Maffini-Alvaro, F. Andrieu, G. LeCarval, P. Vizioz, Y. Campidelli, O. Kermarrec, J. M. Hartmann, S. Borel, V. Delaye, A. Pouydebasque, A. Souifi, P. Coronel, T. Skotnicki, and S. Deleonibus, "3D stacked channels: How series resistances can limit 3D devices performance," in IEEE Int. SOI Conf., 2007, pp. 93-94.
-
(2007)
IEEE Int. SOI Conf
, pp. 93-94
-
-
Bernard, E.1
Ernst, T.2
Guillaumot, B.3
Vulliet, N.4
Maffini-Alvaro, V.5
Andrieu, F.6
LeCarval, G.7
Vizioz, P.8
Campidelli, Y.9
Kermarrec, O.10
Hartmann, J.M.11
Borel, S.12
Delaye, V.13
Pouydebasque, A.14
Souifi, A.15
Coronel, P.16
Skotnicki, T.17
Deleonibus, S.18
-
23
-
-
3943106832
-
Improved split C-V method for effective mobility extraction in sub-0.1 μm Si MOSFETs
-
Aug
-
K. Romanjek, F. Andrieu, T. Ernst, and G. Ghibaudo, "Improved split C-V method for effective mobility extraction in sub-0.1 μm Si MOSFETs," IEEE Electron Device Lett., vol. 25, no. 8, pp. 583-585, Aug. 2004.
-
(2004)
IEEE Electron Device Lett
, vol.25
, Issue.8
, pp. 583-585
-
-
Romanjek, K.1
Andrieu, F.2
Ernst, T.3
Ghibaudo, G.4
-
24
-
-
0023998758
-
New method for the extraction of MOSFETs parameters
-
Apr
-
G. Ghibaudo, "New method for the extraction of MOSFETs parameters," Electron. Lett., vol. 24, no. 9, pp. 543-545, Apr. 1988.
-
(1988)
Electron. Lett
, vol.24
, Issue.9
, pp. 543-545
-
-
Ghibaudo, G.1
-
25
-
-
33745153424
-
Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs
-
F. Andrieu, T. Ernst, F. Lime, F. Rochette, K. Romanjek, S. Barraud, C. Ravit, F. Boeuf, M. Jurczak, M. Casse, O. Weber, L. Brevard, G. Reimbold, G. Ghibaudo, and S. Deleonibus, "Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs," in VLSI Symp. Tech. Dig., 2005, pp. 176-177.
-
(2005)
VLSI Symp. Tech. Dig
, pp. 176-177
-
-
Andrieu, F.1
Ernst, T.2
Lime, F.3
Rochette, F.4
Romanjek, K.5
Barraud, S.6
Ravit, C.7
Boeuf, F.8
Jurczak, M.9
Casse, M.10
Weber, O.11
Brevard, L.12
Reimbold, G.13
Ghibaudo, G.14
Deleonibus, S.15
-
26
-
-
46049114538
-
Unexpected mobility degradation for very short devices: A new challenge for CMOS scaling
-
A. Cros, K. Romanjek, D. Fleury, S. Harrison, C. Cerutti, P. Coronel, B. Dumont, A. Pouydebasque, R. Wacquez, B. Duriez, R. Gwoziecki, F. Boeuf, H. Brut, G. Ghibaudo, and T. Skotnicki, "Unexpected mobility degradation for very short devices: A new challenge for CMOS scaling," in IEDM Tech. Dig., 2006, pp. 663-666.
-
(2006)
IEDM Tech. Dig
, pp. 663-666
-
-
Cros, A.1
Romanjek, K.2
Fleury, D.3
Harrison, S.4
Cerutti, C.5
Coronel, P.6
Dumont, B.7
Pouydebasque, A.8
Wacquez, R.9
Duriez, B.10
Gwoziecki, R.11
Boeuf, F.12
Brut, H.13
Ghibaudo, G.14
Skotnicki, T.15
-
27
-
-
36749009699
-
Carrier mobility degradation due to high dose implantation in ultrathin unstrained and strained silicon-on-insulator films
-
Nov
-
C. Dupré, T. Ernst, J.-M. Hartmann, F. Andrieu, J.-P. Barnes, P. Rivallin, P. F. Fazzini, A. Claverie, F. Cristiano, O. Faynot, S. Cristoloveanu, G. Ghibaudo, and S. Deleonibus, "Carrier mobility degradation due to high dose implantation in ultrathin unstrained and strained silicon-on-insulator films," J. Appl. Phys., vol. 102, no. 10, p. 104 505, Nov. 2007.
-
(2007)
J. Appl. Phys
, vol.102
, Issue.10
, pp. 104-505
-
-
Dupré, C.1
Ernst, T.2
Hartmann, J.-M.3
Andrieu, F.4
Barnes, J.-P.5
Rivallin, P.6
Fazzini, P.F.7
Claverie, A.8
Cristiano, F.9
Faynot, O.10
Cristoloveanu, S.11
Ghibaudo, G.12
Deleonibus, S.13
-
28
-
-
49049087977
-
Impact of isotropic plasma etching on channel Si surface roughness measured by AFM and on NMOS inversion layer mobility
-
C. Dupré, T. Ernst, S. Borel, Y. Morand, S. Descombes, B. Guillaumot, X. Garros, S. Bécu, X. Mescot, G. Ghibaudo, and S. Deleonibus, "Impact of isotropic plasma etching on channel Si surface roughness measured by AFM and on NMOS inversion layer mobility," in Proc. ULIS 2008, pp. 133-136.
-
(2008)
Proc. ULIS
, pp. 133-136
-
-
Dupré, C.1
Ernst, T.2
Borel, S.3
Morand, Y.4
Descombes, S.5
Guillaumot, B.6
Garros, X.7
Bécu, S.8
Mescot, X.9
Ghibaudo, G.10
Deleonibus, S.11
-
29
-
-
36849006875
-
Hydrogen annealing of arrays of planar and vertically stacked Si nanowires
-
Dec
-
E. Dornel, T. Ernst, J. C. Barbé, J. M. Hartmann, V. Delaye, F. Aussenac, C. Vizioz, S. Borel, V. Maffini-Alvaro, C. Isheden, and J. Foucher, "Hydrogen annealing of arrays of planar and vertically stacked Si nanowires," Appl. Phys. Lett., vol. 91, no. 23, p. 233 502, Dec. 2007.
-
(2007)
Appl. Phys. Lett
, vol.91
, Issue.23
, pp. 233-502
-
-
Dornel, E.1
Ernst, T.2
Barbé, J.C.3
Hartmann, J.M.4
Delaye, V.5
Aussenac, F.6
Vizioz, C.7
Borel, S.8
Maffini-Alvaro, V.9
Isheden, C.10
Foucher, J.11
-
30
-
-
55649087741
-
Oxidation of suspended stacked silicon nanowires for sub-10 nm cross-section shape optimization
-
A. Hubert, J.-P. Colonna, S. Bécu, C. Dupré, V. Maffini-Alvaro, J.-M. Hartmann, S. Pauliac, C. Vizioz, F. Aussenac, C. Carabasse, V. Delaye, T. Ernst, and S. Deleonibus, "Oxidation of suspended stacked silicon nanowires for sub-10 nm cross-section shape optimization," ECS Trans., vol. 13, no. 1, pp. 195-199, 2008.
-
(2008)
ECS Trans
, vol.13
, Issue.1
, pp. 195-199
-
-
Hubert, A.1
Colonna, J.-P.2
Bécu, S.3
Dupré, C.4
Maffini-Alvaro, V.5
Hartmann, J.-M.6
Pauliac, S.7
Vizioz, C.8
Aussenac, F.9
Carabasse, C.10
Delaye, V.11
Ernst, T.12
Deleonibus, S.13
-
31
-
-
58049096039
-
A mobility extraction method for 3D multi-channel devices
-
to be published in Solid State Electronics special issue
-
C. Dupré, T. Ernst, E. Bernard, B. Guillaumot, N. Vulliet, P. Coronel, T. Skotnicki, S. Cristoloveanu, G. Ghibaudo, and S. Deleonibus, "A mobility extraction method for 3D multi-channel devices," in Proc. ESSDERC, 2008, pp. 230-233. to be published in Solid State Electronics special issue.
-
(2008)
Proc. ESSDERC
, pp. 230-233
-
-
Dupré, C.1
Ernst, T.2
Bernard, E.3
Guillaumot, B.4
Vulliet, N.5
Coronel, P.6
Skotnicki, T.7
Cristoloveanu, S.8
Ghibaudo, G.9
Deleonibus, S.10
-
32
-
-
3042721855
-
A novel multibridge-channelMOSFET (MBCFET): Fabrication technologies and characteristics
-
Dec
-
S.-Y. Lee, S.-M. Kim, E.-J. Yoon, C.-W. Oh, I. Chung, D. Park, and K. Kim, "A novel multibridge-channelMOSFET (MBCFET): Fabrication technologies and characteristics," IEEE Trans. Nanotechnol., vol. 2, no. 4, pp. 253-257, Dec. 2003.
-
(2003)
IEEE Trans. Nanotechnol
, vol.2
, Issue.4
, pp. 253-257
-
-
Lee, S.-Y.1
Kim, S.-M.2
Yoon, E.-J.3
Oh, C.-W.4
Chung, I.5
Park, D.6
Kim, K.7
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