15nm-diameter 3D stacked nanowires with independent gates operation: φFET

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Dupre C ^a,b   Hubert, A ^a   Becu S ^a   Jublot, M ^a   Maffini Alvaro, V ^a   Vizioz, C ^a   Aussenac, F ^a   Arvet, C ^a,c   Barnola, S ^a   Hartmann, J M ^a   Garnier, G ^a   Allain, F ^a   Colonna, J P ^a   Rivoire, M ^a,c   Baud, L ^a   Pauliac, S ^a   Loup, V ^a   Chevolleau, T ^d   Rivallin, P ^a   Guillaumot, B ^a,c   Ghibaudo, G ^b   Faynot, O ^a   Ernst, T ^a   Deleonibus, S ^a   more..

^a CEA LETI   (France)

^b IMEP LAHC   (France)

^c STMICROELECTRONICS   (France)

^d MINATEC   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL WIDTHS; CMOS TECHNOLOGIES; DRIVING CURRENTS; FIN WIDTHS; FINFETS; GATE STACKS; NANO WIRE STRUCTURES; SUB THRESHOLD SLOPES;

ASPECT RATIO; CMOS INTEGRATED CIRCUITS; ELECTRIC WIRE; ELECTRON DEVICES; MESFET DEVICES; NANOWIRES; TRANSPORT PROPERTIES;

FIELD EFFECT TRANSISTORS;

EID: 64549147010     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796805     Document Type: Conference Paper

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