Distributed flit-buffer flow control for networks-on-chip

Embedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008

Volumn , Issue , 2008, Pages 215-220

  Concer, Nicola ^a,b   Petracca, Michele ^a,c   Carloni, Luca P ^a  

^a Columbia University ^*  (United States)

^b UNIVERSITY OF BOLOGNA   (Italy)

^c POLITECNICO DI TORINO   (Italy)

Author keywords

Latency insensitive protocols; Network on chip

Indexed keywords

BACK PRESSURES; CIRCUIT DESIGNS; CLOCK FREQUENCIES; COMMUNICATION CHANNELS; COMPARATIVE ANALYSIS; EFFECTIVE SOLUTIONS; FLOW CONTROL METHODS; HIGH-LEVEL ABSTRACTIONS; LATENCY-INSENSITIVE PROTOCOLS; LOGIC SYNTHESIS; LOW COMPLEXITY; NETWORK-ON-CHIP; NETWORKS ON CHIPS; NOC DESIGNS; ON CHIPS; PHYSICAL DESIGNS; RELAY STATIONS; ROUTER DESIGNS; RTL DESIGNS; SYSTEM-LEVEL SIMULATIONS; SYSTEMS ON CHIPS; WIRE PIPELINING;

BIOLOGICAL MATERIALS; CODES (SYMBOLS); COMBINES; COMPLEXATION; ELECTRIC NETWORK TOPOLOGY; EMBEDDED SYSTEMS; FLOW CONTROL; INTEGRATED CIRCUITS; LOGIC DESIGN; MICROPROCESSOR CHIPS;

ROUTERS;

EID: 63349088948     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1450135.1450183     Document Type: Conference Paper

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