Zero Skew Clock Routing with Minimum Wirelength

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 39, Issue 11, 1992, Pages 799-814

  Chao, Ting Hai ^a   Hsu, Yu Chin ^b   Ho, Jan Ming ^c   Boese, Kenneth D ^d   Kahng, Andrew B ^d  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c ACADEMIA SINICA   (Taiwan)

^d UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; ELECTRIC NETWORK TOPOLOGY; ELECTRIC WIRING; OPTIMIZATION; TIMING CIRCUITS;

CLOCK SKEW; DESIGN OPTIMIZATION; HIGH SPEED INTERCONNECTS; VLSI DESIGN;

VLSI CIRCUITS;

EID: 0026946698     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.204128     Document Type: Article

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