Process integration of 3D chip stack with vertical interconnection

Proceedings - Electronic Components and Technology Conference

Volumn 1, Issue , 2004, Pages 601-609

  Takahashi, Kenji ^a   Taguchi, Yuichi ^a   Tomisaka, Manabu ^a   Yonemura, Hitoshi ^a   Hoshino, Masataka ^a   Ueno, Mitsuo ^a   Egawa, Yoshimi ^a   Nemoto, Yoshihiko ^a   Yamaji, Yasuhiro ^a   Terao, Hiroshi ^a   Umemoto, Mitsuo ^a   Kameyama, Kojiro ^a   Suzuki, Akira ^a   Okayama, Yoshio ^a   Yonezawa, Toshihiro ^b   Kondo, Kazuo ^b  

^a Assoc Super Adv Electronics T   (Japan)

^b OKAYAMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPOSITION; CURRENT DENSITY; ELECTROPLATING; HEAT LOSSES; MICROPROCESSOR CHIPS; PROJECT MANAGEMENT;

CHEMICAL MECHANICAL PLANARIZATION (CMP); CHIP STACKING STRUCTURE; DEBONDING QUALITY; ULTRA-HIGH-DENSITY PACKAGING;

CHIP SCALE PACKAGES;

EID: 10444221697     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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