KGD production for controlled chip collapse connection (C4) applications

Proceedings - 1998 International Conference on Multichip Modules and High Density Packaging

Volumn 1998-April, Issue , 1998, Pages 362-367

  Atwood, E ^a   Browne, C ^a   Kelly, K ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; COMMERCE; DIES; FLIP CHIP DEVICES; MICROELECTRONICS; MICROPROCESSOR CHIPS; MULTICHIP MODULES; SILICON WAFERS;

APPLICATION REQUIREMENTS; ELECTRONIC ASSEMBLIES; IBM MICROELECTRONICS; KNOWN-GOOD DIES; MAINFRAME SERVERS; QUALITY REQUIREMENTS; SILICON INTEGRATION; WAFER LEVEL TEST;

ASSEMBLY;

EID: 85036818764     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICMCM.1998.670809     Document Type: Conference Paper

References (6)

1. Tummala Rao R., Rymaszewski Eugene R. , editors, "MicroElectronics Packaging Handbook", Van Nostrand Reinhold, N.Y. 1989.
2. Lau John H. editor, "Solder Joint Reliability Theory and Publications", Van Nostrand Reinhold, N.Y. 1991.
3. B. Aimi, R. Antonucci, F. Dimaria, H. Torabi, "Connections Between Circuit Chips and Temporary Carrier for Use in Burnin Tests", U.S. Patent 5, 237, 269, August 17, 1993.
4. G. Beaumont, D. Labbc, A. Warren, "Apparatus and Method for Creating Detachable Soldcr Connections", U.S. Patent, 5, 494, 856 February 27, 1996.
5. Roebuck et al. Patent # 5, 402, 077 Titled Non-Destructive Intcrconnect System for Semi-Conductor Devices
6. Agahdel, F. et al., "Known Good Die Carrier Reliability Evaluation IEEE Intl. Integrated Reliability Workshop, lake Tahoe, Fall 1993