Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs)

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2005, Issue , 2005, Pages 352-355

  Topol, A W ^a   La Tulipe, D C ^a   Shi, L ^a   Alam, S M ^a   Frank, D J ^a   Steen, S E ^a   Vichiconti, J ^a   Posillico, D ^a   Cobb, M ^a   Medd, S ^a   Patel, J ^a   Goma, S ^a   DiMilia, D ^a   Robson, M T ^a   Duch, E ^a   Farinelli, M ^a   Wang, C ^a   Conti, R A ^a   Canaperi, D M ^a   Deligianni, L ^a   Kumar, A ^a   Kwietniak, K T ^a   D'Emic, C ^a   Ott, J ^a   Young, A M ^a   Guarini, K W ^a   Ieong, M ^a   more..

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASSEMBLY; INTEGRATED CIRCUITS; INTERCONNECTION NETWORKS; SILICON WAFERS;

INTERCONNECTION DENSITY; METALLIZATION METHOD; OXIDE FUSION BONDING;

SILICON ON INSULATOR TECHNOLOGY;

EID: 33746910456     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. D. J. Frank, IEDM Tech. Dig. (2002)
2. A. W. Topol et al, ECTC 755 (2004);
3. P. Morrow et al, AMC (2004).
4. K. W. Lee et al, IEDM Tech Dig 165 (2000); A. Fan et al, Electrochem Solid State Lett 2:534 (1999).
5. E. C. Jones and S. W. Bedell, Silicon Wafer Bonding Technology for VLSI and MEMS Applications, INSPEC, London, UK, (2002).
6. K.W. Guarini et al, ICMI 2005;
7. J. Fan, et al., Electrochem. Solid-State Lett. 2, 534 (1999).
8. J.-Q. Lu, et al., AMC, San Diego, CA (2000).
9. A. W. Topol et al, VMIC, Ferment, CA, 3-d (2005);
10. {10] Virginia Semiconductor, Inc.