Different mechanism to explain the 1f noise in n - And p -SOI-MOS transistors fabricated on (110) and (100) silicon-oriented wafers

Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures

Volumn 27, Issue 1, 2009, Pages 394-401

  Gaubert, Philippe ^a   Teramoto, Akinobu ^a   Cheng, Weitao ^a   Hamada, Tatsufumi ^a   Ohmi, Tadahiro ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE COUPLED DEVICES; CLEANING; ELECTRIC CONDUCTIVITY; METALLIC COMPOUNDS; MOS DEVICES; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR MATERIALS; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS; TRANSISTOR TRANSISTOR LOGIC CIRCUITS; TRANSISTORS;

ADVANCED PROCESS; CHANNEL TRANSISTORS; CLEANING PROCESS; DIFFERENT MECHANISMS; HIGH QUALITIES; HIGH-DENSITY PLASMAS; HOOGE MODELS; LOW DENSITIES; LOW-FREQUENCY NOISE; METAL-OXIDE-SEMICONDUCTOR TRANSISTORS; MOS TRANSISTORS; N CHANNELS; N-CHANNEL TRANSISTORS; NOISE LEVELS; SI(1 0 0 ); SI(110);

SEMICONDUCTING SILICON;

EID: 59949098762     PISSN: 10711023     EISSN: None     Source Type: Journal    
DOI: 10.1116/1.3054280     Document Type: Article

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