Dual time-interleaved successive approximation register ADCs for an ultra-wideband receiver

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 2, 2007, Pages 247-257

  Ginsburg, Brian P ^a,b   Chandrakasan, Anantha P ^a,b  

^a IEEE   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

ADC; Analog to digital conversion; CMOS; Scaleable; Successive approximation register; Ultra wideband communication

Indexed keywords

SCALEABLE; SUCCESSIVE APPROXIMATION REGISTER; ULTRA-WIDEBAND COMMUNICATION;

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; NYQUIST DIAGRAMS; SYNTHETIC APERTURE RADAR;

ANALOG TO DIGITAL CONVERSION;

EID: 33847697009     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.889372     Document Type: Article

References (22)

1. A. Batra et al., "Multi-band OFDM physical layer proposal for IEEE 802.15 Task Group 3a," IEEE P802.15-04/0493r0, Sep. 2004 [On-line]. Available: http://grouper.ieee.org/groups/802/15/pub/04/15-04-0493-00-003a- multi-band-ofdm-cfp-document-update.zip
2. R. Fisher et al., "DS-UWB physical layer submission to 802.15 Task Group 3a," IEEE P802.15-04/0137r3, Jul. 2004 [Online]. Available: http://grouper.ieee.org/groups/802/15/pub/04/15-04-0137-04-003a-merger2- proposal-ds-uwb-update.doc
3. D. D. Wentzloff et al., "System design considerations for ultra-wideband communication," IEEE Commun. Mag., vol. 43, no. 8, pp. 114-121, Aug. 2005.
4. P. P. Newaskar, R. Blazquez, and A. P. Chandrakasan, "A/D precision requirements for an ultra-wideband radio receiver," in Proc. IEEE Workshop Signal Processing Systems (SIPS'02), Oct. 2002, pp. 270-275.
5. E. Saberinia, A. H. Twefik, K.-C. Chang, and G. E. Sobelman, "Analog to digital converter resolution of multi-band OFDM and pulsed-OFDM ultra wideband systems," in Proc. 1st Int. Symp. Control, Communications, and Signal Processing, 2004, pp. 787-790.
6. B. P. Ginsburg and A. P. Chandrakasan, "Dual scalable 500MS/s, 5b time-interleaved SAR ADCs for UWB applications," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2005, pp. 10.7.1-10.7.4.
7. K. Yoon, S. Park, and W. Kim, "A 6 b 500 MSample/s CMOS flash ADC with a background interpolated auto-zeroing technique," in IEEE ISSCC Dig. Tech. Papers, 1999, pp. 326-327.
8. Y. Tamba and K. Yamakido, "A CMOS 6 b 500 MSample/s ADC for a hard disk drive read channel," in IEEE ISSCC Dig. Tech.Papers, 1999, pp. 324-325.
9. M. Steyaert, R. Roovers, and J. Craninckx, "A 100 MHz 8 bit CMOS interpolating A/D converter," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 1993, pp. 28.1.1-28.1.4.
10. R. J. van de Plassche and R. E. J. van der Grift, "A high-speed 7 bit A/D converter," IEEE J. Solid-State Circuits, vol. 14, no. 6, pp. 938-943, Dec. 1979.
11. R. C. Taft, C. A. Menkus, M. R. Tursi, O. Hidri, and V. Pons, "A 1.8-V 1.6-GSample/s 8-bit self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2107-2115, Dec. 2004.
12. J. Yuan and C. Svensson, "A 10-bit 5-MS/s successive approximation ADC cell used in a 70-ms/s ADC array in 1.2- μm CMOS," IEEE J. Solid-State Circuits, vol. 29, no. 8, pp. 866-872, Aug. 1994.
13. D. Draxelmayr, "A 6 b 600 MHz 10 mW ADC array in digital 90 nm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2004, pp. 264-265.
14. E. Crain and M. H. Perrott, "A numerical design approach for high speed differential, resistor-loaded CMOS amplifiers," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2004, pp. V-508-V-511.
15. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, Oct. 1989, 10.
16. D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997.
17. B. P. Ginsburg and A. P. Chandrakasan, "An energy-efficient charge recycling approach for a SAR converter with capacitive DAC," in IEEE Int. Symp. Circuits and Systems (ISCAS), 2005, pp. 184-187.
18. J.-B. Shyu, G. C. Temes, and K. Yao, "Random errors in MOS capacitors," IEEE J. Solid-State Circuits, vol. SC-17, no. 6, pp. 1070-1076, Dec. 1982.
19. G. Promitzer, "12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1 MS/s," IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1138-1143, Jul. 2001.
20. J. Montanaro et al., "A 160-MHz, 32-bit, 0.5-W CMOS RISC microprocessor," IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1703-1714, Nov. 1996.
21. J. Doernberg, H.-S. Lee, and D. A. Hodges, "Full-speed testing of A/D converters," IEEE J. Solid-State Circuits, vol. SC-19, no. 6, pp. 820-827, Dec. 1984.
22. F. S. Lee et al., "A 3.1 to 10.6 GHz 100 Mb/s pulse-based ultra-wideband radio receiver chipset," in Proc. IEEE Int. Conf. Ultra-Wideband, 2006, pp. 185-190.