Resistors layout for enhancing yield of R-2R DACS

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2002, Pages

  Lin, Yu ^a   Geiger, Randall ^a  

^a Iowa State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIGITAL TO ANALOG CONVERSION; OPTIMIZATION; RESISTORS;

SHEET RESISTANCE; STANDARD AREA ALLOCATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036297246     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. The art of analog layout
2. Bipolar and MOS analog integrated circuit design
3. Analog VLSI signal and information processing
4. Random error effects in matched MOS capacitors and current sources
5. The design of thin-film polysilicon resistors for analog IC applications
6. Resistor layout techniques for enhancing yield in ratio-critical monolithic applications