A 1.5-V 14-Bit 100-MS/s Self-Calibrated DAC

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 12, 2003, Pages 2051-2060

  Cong, Yonghua ^a,b   Geiger, Randall L ^a  

^a Iowa State University of Science and Technology   (United States)

^b BROADCOM CORPORATION   (United States)

Author keywords

Calibration; CMOS; Digital to analog converter (DAC); High linearity; Low voltage; Self calibration

Indexed keywords

CALIBRATION; CAPACITANCE; CMOS INTEGRATED CIRCUITS; DEGRADATION; DIGITAL CIRCUITS; ELECTRIC IMPEDANCE; ELECTRIC POWER SYSTEMS; ERROR ANALYSIS; LOGIC CIRCUITS; NATURAL FREQUENCIES; OPTIMIZATION; SWITCHING; TRIMMING;

LINEARITY; SELF-CALIBRATION; SPURIOUS FREE DYNAMIC RANGE (SFDR);

DIGITAL TO ANALOG CONVERSION;

EID: 0348233277     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.819163     Document Type: Conference Paper

References (16)

1. J. Vankka, J. Ketola, O. Vaananen, J. Sommarek, M. Kosunen, and K. Halonen, "A GSM/EDGEAVCDMA modulator with on-chip D/A converter for base station," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2002, pp. 236-237.
2. I. Mehr, M. Prabir, and D. Paterson, "A 12-bit integrated analog front end for broadband wireline networks," IEEE J. Solid-State Circuits, vol. 37, pp. 302-309, May 2001.
3. W. Claes, W. Sansen, and A. Puers, "A 40-μ A/channel compensated 18-channel strain gauge measurement system for stress monitoring in dental implants," IEEE J. Solid-State Circuits, vol. 37, pp. 293-301, Mar. 2002.
4. C. Yang, V. Stojanovic, S. Modjtahedi, M. Horowitz, and W. Ellersick, "A serial-link transceiver based on 8-G samples/s A/D and D/A converters in 0.25-μm CMOS," IEEE J. Solid-State Circuits, vol. 36, pp. 293-301, Nov. 2001.
5. J. Wikner and N. Tan, "Modeling of CMOS digital-to-analog converters for telecommunication," IEEE Trans. Circuits Syst. II, vol. 46, pp. 489-499, May 1999.
6. J. Bastos, A. Marques, M. Steyaert, and W. Sansen, "A 12-bit intrinsic accuracy high-speed CMOS DAC," IEEE J. Solid-State Circuits, vol. 33, pp. 1959-1969, Dec. 1998.
7. 2 random walk CMOS DAC," IEEE J. Solid-State Circuits, vol. 34, pp. 1708-11718, Dec. 1999.
8. A. Rugeja and B. Song, "A 14-b, 100-MS/s CMOS DAC designed for spectral performance," IEEE J. Solid-State Circuits, vol. 34, pp. 1719-1731, Dec. 1999.
9. _, "A self-trimming 14-b 100-MS/s CMOS DAC," IEEE J. Solid-State Circuits, vol. 35, pp. 1841-1852, Dec. 2000.
10. J. Bastos, M. Steyaert, and W. Sansen, "A high-yield 12-bit 250-MS/ s CMOS D/A converter," in Proc. IEEE Custom Integrated Circuits Conf., May 1996, pp. 431-434.
11. Y. Cong and R. Geiger, "Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays," IEEE Trans. Circuits Syst. II, vol. 47, pp. 585-595, July 2000.
12. T. Mild, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, "An 80-MHz 8-bit CMOS D/A converter," IEEE, J. Solid-State Circuits, vol. SC-21, pp. 983-988, Dec. 1986.
13. A. Van den Bosch, M. Steyaert, and W. Sansen, "SFDR-bandwidth limitations for high-speed high-resolution current-steering CMOS D/A converters," in Proc. IEEE Int. Conf. Electronics, Circuits and Systems, 1999, pp. 1193-1196.
14. D. Groeneveld, H. Schouwenaars, H. Termeer, and C. Bastiaansen, "A self-calibration technique for monolithic high-resolution D/A converters," IEEE J. Solid-State Circuits, vol. 24, pp. 1517-1522, Dec. 1989.
15. Y. Cong and R. Geiger, "Formulation of INL and DNL yield estimation in current-steering D/A converters," in Proc. IEEE Int. Symp. Circuits and Systems, 2002, pp. 149-152.
16. 2 CMOS DAC," IEEE J. Solid-State Circuits, vol. 36, pp. 1144-1147, July 2001.