Characterization of current-mode CMOS R-2R ladder digital-to-analog converters

IEEE Transactions on Instrumentation and Measurement

Volumn 50, Issue 6, 2001, Pages 1781-1786

  Wang, Lei ^b   Fukatsu, Yasunori ^b   Watanabe, Kenzo ^a,b  

^a IEEE

^b SHIZUOKA UNIVERSITY   (Japan)

Author keywords

CMOS integrated circuit; Current mode; Digital analog conversion; Low power; Resistive ladder

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC LOSSES; ELECTRIC POWER SUPPLIES TO APPARATUS; ERRORS; INTEGRAL EQUATIONS; INTEGRATED CIRCUIT MANUFACTURE;

CURRENT MODE; INTEGRAL NONLINEARITY ANALYSIS; LOW POWER DISSIPATION; POWER CONSUMPTION; RESISTIVE LADDER;

DIGITAL TO ANALOG CONVERSION;

EID: 0035719340     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/19.982980     Document Type: Article

References (10)

1. An inherently linear and compact MOST only current division technique
2. A current-mode approach to CMOS neural network implementation
3. On the robustness of R-2R ladder DAC's
4. Calibration algorithm for current-output R-2R ladders