Investigation of the energy distribution of stress-induced oxide traps by numerical analysis of the TAT of HEs

IEEE Transactions on Electron Devices

Volumn 51, Issue 10, 2004, Pages 1570-1576

  Driussi, Francesco ^a   Iob, Romano ^a   Esseni, David ^a   Selmi, Luca ^a   van Schaijk, Rob ^b   Widdershoven, Frans ^b  

^a UNIVERSITY OF UDINE   (Italy)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRON TRAPS; ENERGY GAP; GATES (TRANSISTOR); LEAKAGE CURRENTS; MATHEMATICAL MODELS; MONTE CARLO METHODS; POISSON DISTRIBUTION; SPECTROSCOPIC ANALYSIS; STRESS ANALYSIS;

SCHROEDINGER-POISSON SOLVER; SUBSTRATE HOT ELECTRON (SHE) INJECTION; TRAP ASSISTED TUNNELING (TAT); TRAP ENERGY DISTRIBUTION;

MOSFET DEVICES;

EID: 5444223661     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.834899     Document Type: Article

References (21)

1. N. Naruke, S. Taguchi, and M. Wada, "Stress-induced leakage current limiting to scale down EEPROM tunnel oxide," in IEDM Tech. Dig., 1988, p. 424.
2. J. De Blauwe, J. Van Houdt, D. Wellekens, G. Groeseneken, and H. E. Maes, "SILC related effects in flash EPROMs - Part I: A quantitative model for steady-state SILC," IEEE Trans. Electron Devices, vol. 45, pp. 1745-1750, Aug. 1998.
3. S. Takagi, N. Yasuda, and A. Toriumi, "Experimental evidence of inelastic tunneling in stress-induced leakage current," IEEE Trans. Electron Devices, vol. 46, pp. 335-341, Feb. 1999.
4. 2 films," IEEE Trans. Electron Devices, vol. 44, p. 1002, June 1997.
5. 2 interface traps in MOS transistors using the charge pumping technique," IEEE Trans. Electron Devices, vol. 44, pp. 2262-2266, Dec. 1998.
6. D. J. DiMaria and E. Cartier, "Mechanism for stress-induced leakage currents in thin silicon dioxide films," J. Appl. Phys., vol. 78, no. 6, pp. 3883-3894, 1995.
7. D. Ielmini, A. Spinelli, M. A. Rigamonti, and A. L. Lacaita, "Modeling of SILC based on electron and hole tunneling - Part I: Transient effects," IEEE Trans. Electron Devices, vol. 47, pp. 1258-1265, June 2000.
8. S. Takagi, N. Yasuda, and A. Toriumi, "A new I-V model for stress-induced leakage current including inelastic tunneling," IEEE Trans. Electron Devices, vol. 46, pp. 348-354, Feb. 1999.
9. L. Larcher, A. Paccagnella, and G. Ghidini, "A model of the stress-induced leakage current in gate oxides," IEEE Trans. Electron Devices, vol. 48, pp. 285-288, Feb 2001.
10. D. Ielmini, A. Spinelli, M. A. Rigamonti, and A. L. Lacaita, "Modeling of SILC-based on electron and hole tunneling - Part II: Steady-state," IEEE Trans. Electron Devices, vol. 47, pp. 1266-1272, June 2000.
11. F. Driussi, R. Iob, D. Esseni, L. Selmi, F. Widdershoven, and R. Schaijk, "Spectroscopic analysis of the TAT in thin oxides by means of substrate hot electron injection experiments," in IEDM Tech. Dig., 2002, pp. 159-162.
12. L. Selmi, B. Fischer, A. Ghetti, and R. Bez, "Hot-carriers at low voltages: New experimental evidences and open issues," in IEDM Tech. Dig., 1996, p. 375.
13. B. Fischer, A. Ghetti, L. Selmi, R. Bez, and E. Sangiorgi, "Bias and temperature dependence of homogeneous hot-electron injection from silicon into silicon dioxide at low voltages," IEEE Trans. Electron Devices, vol. 45, p. 288, Jan., 1997.
14. F. Venturi and A. Ghetti, "Assessment of accuracy limitations of full band MC device simulation," in Proc. SISPAD, 1997, p. 343.
15. D. Esseni, L. Selmi, A. Ghetti, and E. Sangiorgi, "Injection efficiency of CHISEL gate currents in short MOS devices: Physical mechanisms, device implications and sensitivity to technological parameters," IEEE Trans. Electron Devices, vol. 47, p. 2194, Nov. 2000.
16. A. D. Serra, A. Abramo, P. Palestri, L. Selmi, and E. Sangiorgi, "A comparison between semi-classical and quantum-mechanical escape-times for gate current calculations," in Proc. Eur. Solid State Device Res. Conf., 2000, p. 340.
17. P. Palestri, L. Selmi, M. Pavesi, F. Widdershoven, and E. Sangiorgi, "Cathode hot electrons and anode hot holes in tunneling MOS capacitors," in Proc. Eur. Solid State Device Res. Conf., 2000, p. 296.
18. R. Iob, "Simulazione delle correnti di tunnel assistito da trappole in condensatori MOS," Master's thesis, Univ. Udine, Udine, Italy, 2001.
19. S. Takagi, N. Yasuda, and A. Toriumi, "Experimental evidence of inelastic tunneling and new I-V model for stress-induced leakage current," in IEDM Tech. Dig., 1996, p. 323.
20. E. Rosenbaum and J. Wu, "Present understanding of gate oxide wearout," in Proc. Eur. Solid State Device Res. Conf., 2000.
21. W. D. Zhang, J. F. Zhang, M. Lalor, D. Burton, G. V. Groesenekeu, and R. Degraeve, "Two types of neutral electron traps generated in the gate silicon dioxide," IEEE Trans. Electron Devices, vol. 49, pp. 1868-1875, Nov. 2002.