Patterning of narrow porous SiOCH trenches using a TiN hard mask

Microelectronic Engineering

Volumn 85, Issue 11, 2008, Pages 2226-2235

  Darnon, M ^a   Chevolleau, T ^a   Eon, D ^a   Bouyssou, R ^a   Pelissier, B ^a   Vallier, L ^a   Joubert, O ^a   Posseme, N ^a   David, T ^a   Bailly, F ^b   Torres, J ^b  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

Author keywords

Hard mask; Interconnects; Low k; Patterning; TiN

Indexed keywords

ETCHING; INTEGRATED CIRCUITS; LITHOGRAPHY; MATERIALS SCIENCE; PLASMAS; SILICON; SILICON COMPOUNDS; SILICON ON INSULATOR TECHNOLOGY; TIN; TITANIUM COMPOUNDS; TITANIUM NITRIDE;

HARD MASK; INTERCONNECTS; LOW-K; PATTERNING;

TIN DEPOSITS;

EID: 53849108443     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2008.06.025     Document Type: Article

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