Evaluating voltage islands in CMPs under process variations

2007 IEEE International Conference on Computer Design, ICCD 2007

Volumn , Issue , 2007, Pages 129-136

  Das, Abhishek ^a   Ozdemir, Serkan ^a   Memik, Gokhan ^a   Choudhary, Alok ^a  

^a Northwestern University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; LANDFORMS; NETWORKS (CIRCUITS);

COMPUTER DESIGNS; CRITICAL PATHS; DYNAMIC POWER CONSUMPTION; IN-CHIP; INTERNATIONAL CONFERENCES; MAJOR FACTOR; MANUFACTURING TECHNOLOGIES; MULTI-CORE PROCESSORS; ON CHIPS; OPERATING FREQUENCIES; OPTIMAL POWER; PARAMETER VARIATIONS; POWER CONSUMPTION; POWER DISSIPATIONS; POWER SAVINGS; POWER-PERFORMANCE; PROCESS VARIATIONS; SUPPLY VOLTAGES; VARIABLE VOLTAGE; VOLTAGE ISLANDS;

ENERGY CONSERVATION;

EID: 52949088635     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2007.4601891     Document Type: Conference Paper

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