Total leakage optimization strategies for multi-level caches

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2005, Pages 381-384

  Bai, Robert ^a   Kim, Nam Sung ^b   Sylvester, Dennis ^a   Mudge, Trevor ^a  

^a Department of Ecology and Evolutionary Biology   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Cache memory; Gate leakage; Low power

Indexed keywords

LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; OPTIMIZATION; TEMPERATURE;

GATE LEAKAGE; LEAKAGE MECHANISM; LOW POWER;

BUFFER STORAGE;

EID: 29244489805     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1057661.1057752     Document Type: Conference Paper

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