Efficient Adaptive Voltage Scaling System Through On-Chip Critical Path Emulation

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2004-January, Issue January, 2004, Pages 375-380

  Elgebaly, Mohamed ^a   Sachdev, Manoj ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

adaptive voltage scaling; CMOS; Low power

Indexed keywords

CMOS INTEGRATED CIRCUITS; ENERGY EFFICIENCY; LOW POWER ELECTRONICS; POWER ELECTRONICS; VOLTAGE SCALING;

ADAPTIVE VOLTAGE SCALING; CONVENTIONAL SYSTEMS; ENERGY EFFICIENT; INTERCONNECT PARASITICS; LOW POWER; PROCESS VARIATION; PROPOSED ARCHITECTURES; ROBUST OPERATION;

INTEGRATED CIRCUIT TESTING;

EID: 84932165847     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2004.241230     Document Type: Conference Paper

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