Modeling and analysis of parametric yield under power and performance constraints

IEEE Design and Test of Computers

Volumn 22, Issue 4, 2005, Pages 376-385

  Rao, Rajeev R ^a   Blaauw, David ^a   Sylvester, Dennis ^a   Devgan, Anirudh ^b  

^a UNIVERSITY OF MICHIGAN   (United States)

^b MAGMA DESIGN AUTOMATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DESIGN; INTEGRAL EQUATIONS; LEAKAGE CURRENTS; LOGIC GATES; MATHEMATICAL MODELS;

ASIC DESIGN; FULL CHIP LEAKAGE; GATE LEAKAGE;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 24344445513     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2005.89     Document Type: Article

References (12)

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