Design and analysis of a dynamically reconfigurable three-dimensional FPGA

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 1, 2001, Pages 186-196

  Chiricescu, Silviu ^a,b   Leaser, Miriam ^a,c   Michael Vai, M ^a,c  

^a IEEE   (United States)

^b MOTOROLA INC   (United States)

^c Northeastern University   (United States)

Author keywords

Dynamic reconfiguration; Field programmable gate array (FPGA); Three dimensional (3 D) VLSI technology

Indexed keywords

DYNAMIC RECONFIGURATION; LOGIC BLOCK LAYER; MEMORY LAYER; RECONFIGURABLE SYSTEMS; RECONFIGURATION TIME; ROUTING BLOCK LAYER;

FIELD PROGRAMMABLE GATE ARRAYS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LOGIC DEVICES; ROUTERS; THREE DIMENSIONAL; TIME SHARING SYSTEMS; TWO DIMENSIONAL;

VLSI CIRCUITS;

EID: 0035242920     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.920832     Document Type: Article

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