Latch divergency in microprocessor failure analysis

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 755-763

  Dahlgren, Peter ^a   Dickinson, Paul ^a   Parulkar, Ishwar ^a  

^a SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR ANALYSIS; FAILURE ANALYSIS; FLIP FLOP CIRCUITS; LOGIC DESIGN; MICROPROCESSOR CHIPS;

LATCH DIVERGENCE ANALYSIS (LDA);

BUILT-IN SELF TEST;

EID: 0142184774     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. Kinra, A., "Towards Reducing Functional Only Fails for the UltraSPARC Microprocessors", Proc. International Test Conference, 1999, pp. 147-154.
2. Josephson D. et al., "Debug Methodology for the McKinley Processor", Proc. International Test Conference, 2001, pp. 451-460
3. Levitt, M. E., "Testability, Debuggability, and Manufacturability Features of the UltraSPARC™-I Microprocessor", Proc. International Test Conference, 1995, pp. 157-166.
4. Golshan, F., "Test and On-line Debug Capabilities of IEEE Std 1149. 1 in UltraSPARC™-III Microprocessor", Proc. International Test Conference, 2000, pp. 141-150.
5. Parulkar, I., et al., "A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC™ Chip Multi-Processors", Proc. International Test Conference, 2002, pp. 726-734.
6. Hao, H. and Avra, R., "Structured Design-for-Debug - The SuperSPARC II Methodology and Implementation", Proc. International Test Conference, 1995, pp. 175-183.
7. Katz, J., "A Case-Study in the use of Scan in microSPARC™ testing and debug", Proc. International Test Conference, 1994, pp. 456-450.
8. Holdbrook, K. et al., "microSPARC™: A Case-Study of Scan Based Debug", Proc. International Test Conference, 1994, pp. 70-75.
9. Josephson D., "The Manic Depression of Microprocessor Debug", Proc. International Test Conference, 2002, pp. 657-663.