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Volumn , Issue , 2006, Pages 555-562

The UltraSPARC T1 processor: CMT reliability

Author keywords

Channel Hot Carrier (CHC); Chip MultiThreading (CMT); Electromigration (EM); Error Correcting Code (ECC); Gate Oxide Integrity (GOI); Negative Bias Temperature Instability (NBTI); Niagara processor; Reliability, Availability, and Serviceability (RAS)

Indexed keywords

CHANNEL HOT CARRIER (CHC); CHIP MULTITHREADING (CMT); ERROR CORRECTING CODE (ECC);

EID: 33846258518     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2006.320989     Document Type: Conference Paper
Times cited : (29)

References (19)
  • 2
    • 0003158656 scopus 로고
    • Hitting the Memory Wall: Implications of the Obvious
    • March
    • W. A. Wulf and S. A. McKee, "Hitting the Memory Wall: Implications of the Obvious," ACM Computer Architecture News, Vol. 23, No. 1, March 1995, p. 20-24
    • (1995) ACM Computer Architecture News , vol.23 , Issue.1 , pp. 20-24
    • Wulf, W.A.1    McKee, S.A.2
  • 3
    • 39049164252 scopus 로고    scopus 로고
    • Maurice V. Wilkes, The Memory Gap and the Future of High Performance Memories, ATT Research Laboratories - Cambridge, UK (white paper, 2001)
    • Maurice V. Wilkes, "The Memory Gap and the Future of High Performance Memories," ATT Research Laboratories - Cambridge, UK (white paper, 2001)
  • 4
    • 33846231589 scopus 로고    scopus 로고
    • A 32-Way Multithreaded SPARC Processor
    • Stanford, CA, Aug
    • P. Kongetira, "A 32-Way Multithreaded SPARC Processor", presented at 16th Hot Chips Symp., Stanford, CA, Aug., 2004.
    • (2004) presented at 16th Hot Chips Symp
    • Kongetira, P.1
  • 5
    • 20344374162 scopus 로고    scopus 로고
    • A 32-Way Multithreaded SPARC Processor
    • Mar
    • P. Kongetira, et al., "A 32-Way Multithreaded SPARC Processor," in IEEE Micro, Vol. 25. pp. 21-29, Mar., 2005
    • (2005) IEEE Micro , vol.25 , pp. 21-29
    • Kongetira, P.1
  • 7
    • 33846230308 scopus 로고    scopus 로고
    • A Power-Efficient High Throughput 32-Thread SPARC Processor
    • Tech Papers, Feb
    • A. S. Leon, et al., "A Power-Efficient High Throughput 32-Thread SPARC Processor," in IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech Papers, Feb. 2006, pp. 98-99.
    • (2006) IEEE International Solid-State Circuits Conference (ISSCC) Dig , pp. 98-99
    • Leon, A.S.1
  • 8
    • 39049167391 scopus 로고    scopus 로고
    • See the following website for further published measured performance results for the T2000 server: http://www.spec.org/
    • See the following website for further published measured performance results for the T2000 server: http://www.spec.org/
  • 10
    • 0004261043 scopus 로고
    • For further details regarding Weibull Statistics, see:, New York: Van Nostrand Reinhold
    • For further details regarding Weibull Statistics, see: P. A. Tobias and D. Trindade, Applied Reliability. New York: Van Nostrand Reinhold, 1985.
    • (1985) Applied Reliability
    • Tobias, P.A.1    Trindade, D.2
  • 11
    • 19944427720 scopus 로고    scopus 로고
    • A Dual-Core 64-bit UltraSPARC Microprocessor for Dense Server Applications
    • January
    • T. Takayanagi, et al., "A Dual-Core 64-bit UltraSPARC Microprocessor for Dense Server Applications", IEEE Journal of Solid-State Circuits, Vol. 40, No. 1, January 2005.
    • (2005) IEEE Journal of Solid-State Circuits , vol.40 , Issue.1
    • Takayanagi, T.1
  • 13
    • 39049109541 scopus 로고    scopus 로고
    • See the following website for details regarding the Sun Solaris 10 Predictive Self-Healing and Fault Management Software
    • See the following website for details regarding the Sun Solaris 10 Predictive Self-Healing and Fault Management Software: http://opensolaris.org/ os/community/fm/
  • 14
    • 0036927879 scopus 로고    scopus 로고
    • The Impact of Technology Scaling of Soft Error Rate performance and Limits to the Efficacy of Error Correction
    • San Francisco, CA, Dec
    • R. Baumann, "The Impact of Technology Scaling of Soft Error Rate performance and Limits to the Efficacy of Error Correction," in International Electron Device Meeting (IEDM) Tech. Dig., San Francisco, CA, Dec. 2002, pp. 329-332.
    • (2002) International Electron Device Meeting (IEDM) Tech. Dig , pp. 329-332
    • Baumann, R.1
  • 15
    • 29344472607 scopus 로고    scopus 로고
    • Radiation-Induced Soft Errors in Advanced Semiconductor Technologies
    • R. C. Baumann, "Radiation-Induced Soft Errors in Advanced Semiconductor Technologies," in IEEE Trans. Device Material Reliability, vol. 5, no. 3, pp. 305-316, 2005.
    • (2005) IEEE Trans. Device Material Reliability , vol.5 , Issue.3 , pp. 305-316
    • Baumann, R.C.1
  • 16
    • 29344472607 scopus 로고    scopus 로고
    • Radiation-Induced Soft Errors in Advanced Semiconductor Technologies
    • R. C. Baumann, "Radiation-Induced Soft Errors in Advanced Semiconductor Technologies," in IEEE Trans. Device Material Reliability, vol. 5, no. 3, pp. 305-316, 2005.
    • (2005) IEEE Trans. Device Material Reliability , vol.5 , Issue.3 , pp. 305-316
    • Baumann, R.C.1
  • 18
    • 39049132808 scopus 로고    scopus 로고
    • Multi-core SoCs, Test and Yield Enhancement Challenges and Solutions
    • presented at, San Francisco, CA
    • J. Rosal, "Multi-core SoCs, Test and Yield Enhancement Challenges and Solutions," presented at Microprocessor Forum, IEEE Int. Solid-State Circuits Conf., San Francisco, CA 2006
    • (2006) Microprocessor Forum, IEEE Int. Solid-State Circuits Conf
    • Rosal, J.1
  • 19
    • 39049137354 scopus 로고    scopus 로고
    • Testing of UltraSPARC T1 Microprocessor and its Challenges
    • submitted to International Test Conference
    • P. J. Tan, et al., "Testing of UltraSPARC T1 Microprocessor and its Challenges," submitted to International Test Conference 2006.
    • (2006)
    • Tan, P.J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.