Low-power algorithm for automatic topology generation for application-specific networks on chips

IET Computers and Digital Techniques

Volumn 2, Issue 3, 2008, Pages 239-249

  Chang, K C ^a   Chen, T F ^b  

^a FENG CHIA UNIVERSITY   (Taiwan)

^b NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATIONS; CELLULAR TELEPHONE SYSTEMS; COMPUTER ARCHITECTURE; ELECTRIC NETWORK TOPOLOGY; LARGE SCALE SYSTEMS; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; POWER GENERATION; SYSTEMS ENGINEERING; TELECOMMUNICATION; TELECOMMUNICATION EQUIPMENT; TELEPHONE SYSTEMS; TOPOLOGY;

(OTDR) TECHNOLOGY; APPLICATION SPECIFIC SYSTEMS; APPLICATION-SPECIFIC; AUTOMATIC TOPOLOGY; CASE STUDIES; COMMUNICATION STRUCTURES; COMMUNICATIVE COMPONENTS; EXPERIMENTAL RESULTS; GENERAL (CO); INTERCONNECTION ARCHITECTURES; INTERCONNECTION TOPOLOGIES; IRREGULAR NETWORKS; LARGE SCALES; LOW POWERS; MULTIMEDIA APPLICATIONS; NETWORKS ON CHIP (NOCS); OVERALL POWER; PHONE SYSTEMS; POWER SAVINGS; POWER-AWARE; REGULAR NETWORKS; TOPOLOGY CONSTRUCTION; TRAFFIC CHARACTERISTICS;

ENERGY CONSERVATION;

EID: 46649092517     PISSN: 17518601     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cdt:20070049     Document Type: Article

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