Joint application mapping/interconnect synthesis techniques for embedded chip-scale multiprocessors

IEEE Transactions on Parallel and Distributed Systems

Volumn 16, Issue 2, 2005, Pages 99-112

  Bambha, Neal K ^a   Bhattacharyya, Shuvra S ^b  

^a U S ARMY RESEARCH LABORATORY   (United States)

^b UNIVERSITY OF MARYLAND   (United States)

Author keywords

Embedded multiprocessors; Interconnect synthesis; Scheduling; Task graphs

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; CONSTRAINT THEORY; DIGITAL SIGNAL PROCESSING; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; OPTICAL INTERCONNECTS; PROBABILITY; TRANSISTORS;

EMBEDDED MULTIPROCESSORS; INTERCONNECT SYNTHESIS; SCHEDULING ALGORITHMS; TASK GRAPHS;

MULTIPROCESSING SYSTEMS;

EID: 14844356932     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPDS.2005.20     Document Type: Article

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