Scalar operand networks: On-chip interconnect for ILP in partitioned architectures

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn 12, Issue , 2003, Pages 341-353

  Bedford Taylor, M ^a   Lee, W ^a   Amarasinghe, S ^a   Agarwal, A ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Computer industry; Counting circuits; Delay; Distributed computing; Microprocessors; Network on a chip; Pipelines; Registers; Scalability; System recovery

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SYSTEM RECOVERY; COUNTING CIRCUITS; INTEGRATED CIRCUIT INTERCONNECTS; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; NETWORKS (CIRCUITS); PIPELINES; SCALABILITY; SUPERCOMPUTERS;

COMPUTER INDUSTRY; DELAY; NETWORK ON A CHIP; REGISTERS; SYSTEM RECOVERY;

DISTRIBUTED COMPUTER SYSTEMS;

EID: 84955456130     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2003.1183551     Document Type: Conference Paper

References (21)

1. AGARWAL, HRISHIKESH, KECKLER, BURGER. Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures. In International Symposium on Computer Architecture (2000) .
2. ARVIND, BROBST. The Evolution of Dataflow Architectures from Static Dataflow to P-RISC. International Journal of High Speed Computing 5, 2 (June 1993).
3. BABB ET AL. The RAW Benchmark Suite: Computation Structures for General Purpose Computing. In IEEE Symposium on Field-Programmable Custom Computing Machines ( 1 997 ) .
4. BARUA, LEE, AMARASINGHE, AGARWAL. Maps: A Compiler-Managed Memory System for Raw Machines. In International Symposium on Computer Architecture ( 1 999).
5. DALLY. A VLSI Architecture for Concurrent Data Structures. Kluwer Academic Publishers, 1997.
6. GROSS, OHALLORON . Warp, Anatomy of a Parallel Computing System. The MIT Press, Cambridge, MA, 199B.
7. GWENNAP. Digital 2 1 264 Sets New Standard. Microprocessor Report (October 2B, 1996) .
8. JANSSEN, CORPORAAL. Partitioned Register File for TTAs. In International Symposium on Microarchitecture ( 1996) .
9. KIM, SMITH. An Instruction Set Architecture and Microarchitecture for Instruction Level Distributed Processing. In International Symposium on Computer Architecture (2002).
10. KUBIATOWICZ, AGARWAL. Anatomy of a Message in the Alewife Multiprocessor. In International Supercomputing Conference ( 1 993).
11. LARSEN, AMARASINGHE. Increasing and Detecting Memory Address Congruence. In International Conference on Parallel Architectures and Compilation Techniques (2002).
12. LEE ET AL. Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine. In Conference on Architectural Support for Programming Languages and Operating Systems ( 1 99B ) .
13. MAL, PAASKE, JAYASENA, Ho , DALLY, HOROWITZ. Smart Memories: A Modular Reconfigurable Architecture. In International Symposium on Computer Architecture (2000) .
14. NAFFZIGER, HAMMOND. The Implementation of the Next-Generation 64b Itanium Microprocessor. In IEEE International Solid-State Circuits Conference (2002) .
15. NAGARAJAN, SANKARALINGAM , BURGER, KECKLER. A Design Space Evaluation of Grid Processor Architectures. In International Symposium on Microarchitecture (200 1 ) .
16. PALACHARLA, JOUPPI, SMITH. Complexity-Effective Superscalar Processors. In International Symposium on Computer Architecture ( 1 997 ) .
17. SCALE. http://www.cag.lcs.mit.edu/scale/overview.html/, 2002.
18. SOHI, BREACH, VIJAY KUMAR. Multiscalar Processors. In International Symposium on Computer Architecture ( 1 995 ) .
19. TAYLOR. The Raw Processor Specification. http://ftp. cag. lcs. mit. edu/pub/raw/documents/RawSpec99 . pdf.
20. TAYLOR, LEE, FRANK, AGARWAL, AMARASINGHE. How to Build Scalable On-Chip ILP Networks for a Decentralized Architecture. Tech. Rep. 62B, MIT, April 2000.
21. TAYLOR ET AL. The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Prgrams. IEEE Micro (March 2002).