An instruction set and microarchitecture for instruction level distributed processing

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 2002, Pages 71-81

  Kim, Ho Seop ^a   Smith, James E ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DISTRIBUTED COMPUTER SYSTEMS; FILE ORGANIZATION; HIERARCHICAL SYSTEMS; NATURAL FREQUENCIES; PIPELINE PROCESSING SYSTEMS; TIMING CIRCUITS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

INSTRUCTION SET ARCHITECTURES (ISA); SUPERSCALAR PROCESSORS;

MICROPROCESSOR CHIPS;

EID: 0036292594     PISSN: 08847495     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCA.2002.1003563     Document Type: Article

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