The revolution inside the box

Communications of the ACM

Volumn 51, Issue 7, 2008, Pages 70-78

  Oskin, Mark ^a  

^a UNIVERSITY OF WASHINGTON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE RESEARCH; COMPUTING CAPABILITIES; DESKTOP COMPUTING; INFORMATION TECHNOLOGY (IT); INTERNATIONAL SYMPOSIUM; IT BUSINESS; MAINSTREAM (MS); MEMORY WALL; MULTI CORES; PERFORMANCE IMPROVEMENTS; PROGRAMMING MODELS; SCALABLE PERFORMANCE; SOFTWARE COMPANIES; SOFTWARE DEVELOPERS; USER EXPERIENCE;

COMPUTER SCIENCE; COMPUTER SYSTEMS; COMPUTERS; GRAPHIC METHODS; INDUSTRY; PARALLEL PROGRAMMING; TECHNOLOGY;

COMPUTER ARCHITECTURE;

EID: 46249092556     PISSN: 00010782     EISSN: 15577317     Source Type: Journal    
DOI: 10.1145/1364782.1364799     Document Type: Article

References (46)

1. Agarwal, V., Hrishikesh, M.S., Keckler, S.W., and Burger, D. Clock rate versus IPC: The end of the road for conventional microarchitectures. SIGARCH Comput. Archit. News 28, 2, (2000), 248-259.
2. Austin, T.M. Diva: A reliable substrate for deep submicron microarchitecture design. Micro. 00 196, 1999.
3. Borch, E. Tune, E., Manne, S., and Emer, J. Loose loops sink chips. In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture. Feb. 2-6, 2002, 299-310.
4. th Annual IEEE/ ACM International Symposium on Microarchitecture. IEEE Computer Society, Washington, D.C., 2004, 18-29.
5. Brooks, D., Tiwari, V., and Martonosi, M. Wattch: A framework for architectural-level power analysis and optimizations. SIGARCH Comput. Archit. News 28, 2, (2000), 83-94.
6. Brooks, D.M., Bose, P., Schuster, S.E. Jacobson, H., Kudva, P.N. Buyuktosunoglu, A., Wellman, J-D., Zyuban, V., Gupta, M., and Cook, P.W. Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors. IEEE Micro 20, 6 (2000), 26-44.
7. Burger, D., and Austin, T.M. The simplescalar tool set, version 2.0. SIGARCH Comput. Archit. News 25, 3 (1997), 13-25.
8. Ceze, L., Tuck, J., Montesinos, P., and Torrellas, J. Bulksc: Bulk enforcement of sequential consistency. SIGARCH Comput. Archit. News 35, 2 (2007), 278-289.
9. Cristal, A., Ortega, D., Llosa, J., and Valero, M. Out-of-order commit processors. hpca, 00:48, 2004.
10. Dagum, R., Menon, L. Openmp: An industry standard api for shared-memory programming. Computational Science and Engineering 5, 11, (Jan-Mar 1998) 46-55.
11. th International Conference on Supercomputing., ACM, NY, 2002, 14-25.
12. st Annual ACM/IEEE International Symposium on Microarchitecture (Nov. 30-Dec. 2, 1998), 69-77.
13. Eeckhout, L., Stougie, B., Bosschere, K.D., and John, L.K. Control flow modeling in statistical simulation for accurate and effcient processor design studies. SIGARCH Comput. Archit. News 32, 2 (2004), 350.
14. th Annual International Symposium on Computer Architecture (June 9-11, 2003), 253-262.
15. th Annual International Symposium on Computer Architecture (Los Alamitos, CA, 1983). IEEE Computer Society Press, 140-150.
16. Hill, M.D. Multiprocessors should support simple memory-consistency models. IEEE Computer 31, 8 (1998), 28-34.
17. Hinton, G., Upton, M., Sager, D., Boggs, D., Carmean, D., Roussel, P., Chappell, T., Fletcher, T., Milshtein, M., Sprague, M., Samaan, S., and Murray., R. A 0.18-m CMOS ia-32 processor with a 4-ghz integer execution unit. IEEE Journal of Solid-State Circuits, 36, 11 (Nov. 2001),1617-1627.
18. Jouppi, N.P. Improving direct-mapped cache performance by the addition of a small fully associative cache and prefetch buffers. SIGARCH Comput. Archit. News, 18, 3a (1990), 364-373.
19. Kang, Y., Huang, W., Yoo, S.-M., Keen, D., Ge, Z., Lam, V., Torrellas, J., and Pattnaik, P. Flexram: Toward an advanced intelligent memory system. ICCD 00:192, 1999.
20. Kogge, P., Sunaga, T., Miyataka, H., Kitamura, K., and Retter, E. Combined DRAM and logic chip for massively parallel systems. arvlsi 0:4, 1995.
21. th Annual International Symposium on Computer Architecture. ACM, NY, 1992, 46-57.
22. McNairy, D., Soltis, C. Itanium 2 processor microarchitecture. IEEE Micro 23, 2 (Mar.-Apr. 2003), 44-55,
23. Moore, G. Cramming more components onto integrated circuits. Electronics (Apr. 1965), 114-117.
24. th Annual International Symposium on Computer Architecture (2002), 99-110.
25. th Annual IEEE/ACM International Symposium on Microarchitecture (Dec. 3-5, 2003), 29-40.
26. th Annual ACM/IEEE International Symposium on Microarchitecture. IEEE Computer Society, Washington, D.C. 2001, 40-51.
27. Nielsen, L.S., and Niessen, C. Low-power operation using self-timed circuits and adaptive scaling of the supply voltage. IEEE Trans. Very Large Scale Integr. Syst., 2, 4 (1994), 391-397.
28. Oskin, M., Chong, F.T., and Farrens, M. HlS: Combining statistical and symbolic simulation to guide microprocessor designs. SIGARCH Comput. Archit. News 28, 2 (2002), 71-82.
29. Oskin, M., Chong, F.T., and Sherwood, T. Active pages: A computation model for intelligent memory. SIGARCH Comput. Archit. News 26, 3 (1998), 192-203.
30. Pai, V.S., Ranganathan, P., Adve, S.V., and Harton, T. An evaluation of memory consistency models for shared-memory systems with ilp processors. SIGPLAN Notices 31, 9 (1996), 12-23.
31. Palacharla, S. Complexity-effective superscalar processors. Ph.D. thesis, 1998.
32. Patterson, D., Anderson, T., Cardwell, N., Fromm, R., Keeton, K., Kozyrakis, C., Thomas, R., and Yelick, K. A case for intelligent RAM. IEEE Micro 17, 2 (Mar.-Apr. 1997), 34-44.
33. Patterson, D., Keutzer, K., Asanovic, K., Yelick, K., and Bodik, R. The landscape of parallel computing research: A view from Berkeley. 2007.
34. Pollack, F., Keynote: New microarchitecure challenges in the coming generations of CMOS process technologies, 1999.
35. th International Conference on Architectural Support for Programming Languages and Operating Systems. ACM, NY, 2002, 45-57.
36. th Annual IEEE/ ACM International Symposium on Microarchitecture. IEEE Computer Society, Washington, D.C., 291.
37. Taylor, M.B., Kim, J., Miller, J., Wentzlaff, D., Ghodrat, F., Greenwald, B., Hoffman, F., Johnson, P., Lee, J.-W., Lee, W., Ma, A., Saraf, A., Seneski, M., Shnidman, N., Strumpen, V., Frank, M., Amarasinghe, S., and Agarwal, A. The raw microprocessor: A computational fabric for software circuits and general-purpose programs. IEEE Micro 22, 2 (2002), 25-35.
38. Valero, M., Gonzalez, A., Topham, N.P., and Cruz, C. Multiple-banked register fle architectures. isca 00:316, 2000.
39. th Annual International Symposium on Computer Architecture (2002), 87-98.
40. Wawrzynek, J., Patterson, D., Oskin, M., Lu, S.-L., Kozyrakis, C., Hoe, J. C., Chiou, D., and Asanovi, K. RAMP: Research accelerator for multiple processors. IEEE Micro 27, 2 (2007), 46-57.
41. th Annual International Symposium on Computer Architecture (June 9-11, 2003), 84-95.
42. th Conference on Design Automation. ACM, NY (2000), 340-345
43. http://www.news.com/2100-1006 3-6119618.html.
44. http://www.itrs.net/.
45. http://pages.cs.wisc.edu/ markhill/mp2001.html.
46. Personal communication with Burton Smith.