A 0.18-μm CMOS IA-32 processor with a 4-GHz integer execution unit

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 11, 2001, Pages 1617-1627

  Hinton, Glenn ^b   Upton, Michael ^b   Sager, David J ^a,b   Boggs, Darrell ^b   Carmean, Douglas M ^b   Roussel, Patrice ^b   Chappell, Terry I ^a,b   Fletcher, Thomas D ^b   Milshtein, Mark S ^a,b   Sprague, Milo ^b   Samaan, Samie ^b   Murray, Robert ^b  

^a IEEE

^b INTEL CORPORATION   (United States)

Author keywords

Adders; Clocks; CMOS digital integrated circuits; Computer architecture; High speed integrated circuits; Memory architecture; Pipelines

Indexed keywords

ADDERS; CACHE MEMORY; CLOCKS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; INTEGRATED CIRCUIT LAYOUT; MULTIMEDIA SYSTEMS;

ARITHMETIC LOGIC UNIT; DATA CACHE; HIGH SPEED INTEGRATED CIRCUITS; MEMORY ARCHITECTURE; TRACE CACHE;

MICROPROCESSOR CHIPS;

EID: 6644229433     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.962281     Document Type: Article

References (7)

1. A high-performance 180-nm generation logic technology
2. Multi-GHz clocking scheme for Intel® Pentium® 4 microprocessor
3. A 0.18-μm CMOS IA-32 microprocessor with a 4-GHz integer execution unit
4. Self-resetting logic register and incrementer
5. Backside infrared probing for static voltage drop and dynamic timing measurements