RAMP: Research accelerator for multiple processors

IEEE Micro

Volumn 27, Issue 2, 2007, Pages 46-57

  Wawrzynek, John ^a   Patterson, David ^a   Oskin, Mark ^b   Lu, Shih Lien ^c   Kozyrakis, Christoforos ^d   Hoe, James C ^e   Chiou, Derek ^f   Asanović, Krste ^g  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF WASHINGTON   (United States)

^c INTEL CORPORATION   (United States)

^d STANFORD UNIVERSITY   (United States)

^e CARNEGIE MELLON UNIVERSITY   (United States)

^f UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^g Department of Electrical Engineering and Computer Science   (United States)

Author keywords

Distributed systems; Distributed shared memory; Emulation; Field programmable gate arrays; Hardware software codesign; Integration; Modeling of computer architecture; Parallel architectures; Transactional memory

Indexed keywords

COMPUTER ARCHITECTURE; DISTRIBUTED COMPUTER SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MOBILE COMPUTING; PARALLEL PROCESSING SYSTEMS;

DISTRIBUTED-SHARED MEMORY; HARDWARE-SOFTWARE CODESIGN; PARALLEL ARCHITECTURES; TRANSACTIONAL MEMORY;

COMPUTER NETWORKS;

EID: 34548253874     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2007.39     Document Type: Conference Paper

References (6)

1. G. Gibeling, A. Schultz, and K. Asanovic, "RAMP Architecture and Description Language," 2nd Workshop Architecture Research Using FPGA Platforms, 2006; http://cag.csail.mit.edu/~krste/papers/ rampgateware-warfp2006.pdf.
2. C. Chang, J. Wawrzynek, and R.W. Brodersen, "BEE2: A High-End Reconfigurable Computing System," IEEE Design & Test, vol. 22, no. 2, Mar.-Apr. 2005, pp. 114-125.
3. A.-R. Adl-Tabatabai, C. Kozyrakis, and B. Saha, "Unlocking Concurrency: Multicore Programming with Transactional Memory," ACM Queue, vol. 4, no. 10, Dec. 2006; http://acmqueue.com/ modules.php?name=Content&pa=showpage&pid=444.
4. L. Hammond et al., "Programming with Transactional Coherence and Consistency (TCC)," Proc. 11th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 04), ACM Press, 2004, pp. 1-13.
5. S. Wee et al., "A Practical FPGA-Based Framework for Novel CMP Research," Proc. 15th ACM/SIGDA Int'l Symp. Field-Programmable Gate Arrays (FPGA 07), ACM Press, 2007, pp. 116-125.
6. B.D. Carlstrom et al., "The Software Stack for Transactional Memory: Challenges and Opportunities," First Workshop on Software Tools for Multicore Systems (STMCS 06), 2006; http://ogun.stanford.edu/~kunle/ publications/tcc_stmcs2006.pdf.