On circuit techniques to improve noise immunity of CMOS dynamic logic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 9, 2004, Pages 910-925

  Ding, Li ^a   Mazumder, Pinaki ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Digital integrated circuits; Domino logic style; Dynamic circuits; Negative differential resistance; Noise tolerant design

Indexed keywords

COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; LOGIC CIRCUITS; LOGIC DESIGN; LOGIC GATES; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

DOMINO LOGIC STYLES; DYNAMIC CIRCUITS; NEGATIVE DIFFERENTIAL RESISTANCE; NOISE TOLERANT DESIGN;

CMOS INTEGRATED CIRCUITS;

EID: 4544274990     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.833668     Document Type: Article

References (34)

1. P. Larsson and C. Svensson, "Noise in digital dynamic CMOS circuits," IEEE J. Solid-State Circuits, vol. 29, pp. 655-662, June 1994.
2. K. L. Shepard and V. Narayanan, "Noise in deep submicron digital design," in Proc. Int. Conf. Computer Aided Design, 1996, pp. 524-531.
3. R. H. Krambeck, C. M. Lee, and H.-F. S. Law, "High-speed compact circuits with CMOS," IEEE J. Solid-State Circuits, vol. SC-17, pp. 614-619, June 1982.
4. V. G. Oklobdzija and R. K. Montoye, "Design-performance trade-offs in CMOS domino logic," in Proc. IEEE Custom Integrated Circuits Conf., May 1985, pp. 334-337.
5. M. H. Anis, M. W. Allam, and M. I. Elmasry, "High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies," in Proc. Int. Symp. Low-Power Electronics and Design, 2000, pp. 155-160.
6. _, "Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies," IEEE Trans. VLSI Syst., vol. 10, pp. 71-78, Apr. 2002.
7. A. Alvandpour, R. K. Krishnamurthy, K. Soumyanath, and S. Y. Borkar, "A conditional keeper technique for sub-0.13μ wide dynamic gates," in Proc. Int. Symp. VLSI Circuits, 2001, pp. 29-30.
8. _, "A sub- 130-nm conditional keeper technique," IEEE J. Solid-State Circuits, vol. 37, pp. 633-638, May 2002.
9. C. M. Lee and E. W. Szeto, "Zipper CMOS," IEEE Circuits Devices Mag., vol. 2, pp. 10-17, May 1986.
10. J. A. Pretorius, A. S. Shubat, and C. A. T. Salama, "Charge redistribution and noise margins in domino CMOS logic," IEEE Trans. Circuits Syst., vol. CAS-33, pp. 786-793, Aug. 1986.
11. G. P. D'Souza, "Dynamic logic circuit with reduced charge leakage," U.S. Patent 5483 181, Jan. 1996.
12. E. B. Schorn, "NMOS charge-sharing prevention device for dynamic logic circuits," U.S. Patent 5 838 169, Nov. 1998.
13. L. Wang and N. R. Shanbhag, "Noise-tolerant dynamic circuit design," in Proc. Int. Symp. Circuits Systems, 1999, pp. 1549-552.
14. _, "An energy-efficient noise-tolerant dynamic circuit technique," IEEE Trans. Circuits Syst. II, vol. 47, pp. 1300-1306, Nov. 2000.
15. G. Balamurugan and N. R. Shanbhag, "Energy-efficient dynamic circuit design in the presence of crosstalk noise," in Proc. Int. Symp. Low-Power Electronics and Design, 1999, pp. 24-29.
16. _, "The twin-transistor noise-tolerant dynamic circuit technique," IEEE J. Solid-State Circuits, vol. 36, pp. 273-280, Feb. 2001.
17. F. Murabayashi et al., "2.5 V novel CMOS circuit techniques for a 150 MHz superscalar RISC processor," in Proc. Eur. Solid-State Circuits Conf., 1995, pp. 178-181.
18. F. Murabayashi et al., "2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor," IEEE J. Solid-State Circuits, vol. 31, pp. 972-980, July 1996.
19. J. J. Covino, "Dynamic CMOS circuits with noise immunity," U.S. Patent 5 650 733, July 1997.
20. D. A. Evans, "Noise-tolerant dynamic circuits," U.S. Patent 5793 228, Aug. 1998.
21. S. Bobba and I. N. Hajj, "Design of dynamic circuits with enhanced noise tolerance," in Proc. IEEE Int. ASIC/SOC Conf., 1999, pp. 54-58.
22. C.-Y. Wu and K.-N. Lai, "Integrated Λ -type differential negative resistance MOSFET device," IEEE J. Solid-State Circuits, vol. SC-14, pp. 1094-1101, Dec. 1979.
23. C.-Y. Wu and C.-Y. Wu, "The new general realization theory of FET-like integrated voltage-controlled negative differential resistance devices," IEEE Trans. Circuits Syst., vol. CAS-28, no. 5, pp. 382-390, May 1981.
24. L. O. Chua, J. Yu, and Y. Yu, "Bipolar-JFET-MOSFET negative resistance devices," IEEE Trans. Circuits Syst., vol. CAS-32, pp. 46-61, Jan. 1985.
25. K. K. Ng, "A survey of semiconductor devices," IEEE Trans. Electron Devices, vol. 43, pp. 1760-1766, Oct. 1996.
26. L. G. Heller, W. R. Griffin, J. W. Davis, and N. G. Thoma, "Cascode voltage switch logic: A differential CMOS logic family," in Proc. Int. Solid-State Circuit Conf., Feb. 1984, pp. 16-17.
27. M. Bhattacharya and P. Mazumder, "Noise margins of threshold logic gates containing resonant tunneling diodes," IEEE Trans. Circuits Syst. II, vol. 47, pp. 1080-1085, Oct. 2000.
28. J.-P. Sun, G. I. Haddad, P. Mazumder, and J. N. Schulman, "Resonant tunneling diodes: Models and properties," Proc. IEEE, vol. 86, pp. 641-660, Apr. 1998.
29. P. Mazumder, S. Kulkarni, M. Bhattacharya, J.-P. Sun, and G. I. Haddad, "Digital circuit applications of resonant tunneling devices," Proc. IEEE, vol. 86, pp. 664-686, Apr. 1998.
30. K. J. Chen, K. Maezawa, and M. Yamamoto, "A novel ultrafast functional device: Resonant tunneling high electron mobility transistor," in Proc. IEEE Electron Devices Meeting, 1996, pp. 60-63.
31. J. Stock, J. Malindretos, K. M. Indlekofer, M. Pottgens, A. Forster, and H. Luth, "A vertical resonant tunneling transistor for application in digital logic circuits," IEEE Trans. Electron Devices, vol. 48, pp. 1028-1032, June 2001.
32. S. Mohan, J. P. Sun, P. Mazumder, and G. I. Haddad, "Device and circuit simulation of quantum electronic devices," IEEE Trans. Computer-Aided Design., vol. 14, pp. 653-662, June 1995.
33. S. K. Sunter, "Current-mirror-biased pre-charged logic circuit," U.S. Patent 4 797 580, Jan. 1989.
34. J. M. Daga and D. Auvergne, "A comprehensive delay macro modeling for submicrometer CMOS logics," IEEE J. Solid-State Circuits, vol. 34, pp. 42-55, Jan. 1999.