2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 7, 1996, Pages 972-979

  Murabayashi, Fumio ^b,c,d   Yamauchi, Tatsumi ^b   Yamada, Hiromichi ^b,e,f   Nishiyama, Takahiro ^b,g   Shimamura, Kotaro ^b,g   Tanaka, Shigeya ^b,h   Hotta, Takashi ^a,b,g   Shimizu, Teruhisa ^b   Sawamoto, Hideo ^b  

^a IEEE

^b HITACHI LTD   (Japan)

^c MIE UNIVERSITY   (Japan)

^d TOHOKU UNIVERSITY

^e SAGA UNIVERSITY   (Japan)

^f KYUSHU UNIVERSITY   (Japan)

^g UNIVERSITY OF TOKYO   (Japan)

^h TOYOHASHI UNIVERSITY OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; DELAY CIRCUITS; ELECTRIC LOSSES; ELECTRIC WIRING; GATES (TRANSISTOR); LEAKAGE CURRENTS; LOGIC GATES; PERFORMANCE; REDUCED INSTRUCTION SET COMPUTING; SPURIOUS SIGNAL NOISE; SUPERCOMPUTERS; TRANSISTORS;

FLOATING POINT MACROCELL; FLOATING POINT REGISTERS; GATE DELAY TIME; NMOS TRANSMISSION GATE; NOISE TOLERANT PRECHARGE CIRCUIT; SIGNAL WIRING; SUPERSCALAR RISC PROCESSOR;

CMOS INTEGRATED CIRCUITS;

EID: 0030192452     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.508211     Document Type: Article

References (11)

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