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Volumn 36, Issue 2, 2001, Pages 273-280

The twin-transistor noise-tolerant dynamic circuit technique

Author keywords

CMOS integrated circuits; Crosstalk; Dynamic circuits; Noise; Noise tolerant design

Indexed keywords

CMOS INTEGRATED CIRCUITS; CROSSTALK; MULTIPLYING CIRCUITS; POWER SUPPLY CIRCUITS; SPURIOUS SIGNAL NOISE; THROUGHPUT;

EID: 0035247081     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.902768     Document Type: Article
Times cited : (59)

References (20)
  • 1
  • 14
    • 0005281249 scopus 로고    scopus 로고
    • "Dynamic CMOS circuits with noise immunity"U.S. Patent 5 650 733, July 22, 1997
    • Covino, J.J.1
  • 15
    • 0005388159 scopus 로고    scopus 로고
    • "Dynamic logic circuit with reduced charge leakage," U.S. Patent 5 483 181, Jan. 1996
    • D'Souza, G.P.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.