Energy-efficient dynamic circuit design in the presence of crosstalk noise

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 24-29

  Balamurugan, Ganesh ^a   Shanbhag, Naresh R ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CROSSTALK; ELECTRIC POTENTIAL; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; SPURIOUS SIGNAL NOISE;

NOISE TOLERANCE TECHNIQUES;

CMOS INTEGRATED CIRCUITS;

EID: 0033362676     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/313817.313833     Document Type: Article

References (16)