Technology mapping and cell merger for asynchronous threshold networks

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 4, 2008, Pages 659-672

  Jeong, Cheoljoo ^a,b,c   Nowick, Steven M ^a,b  

^a IEEE

^b Department of Earth and Environmental Sciences   (United States)

^c CADENCE DESIGN SYSTEMS   (United States)

Author keywords

Asynchronous threshold networks; Cell merger; Delay insensitive encoding; Logic synthesis; Technology mapping

Indexed keywords

AUTOMATION; COST FUNCTIONS; OPTIMIZATION; PROBLEM SOLVING; ROBUST CONTROL; ROBUSTNESS (CONTROL SYSTEMS);

ASYNCHRONOUS THRESHOLD NETWORKS; DELAY-INSENSITIVE ENCODING; LOGIC SYNTHESIS; TECHNOLOGY MAPPING;

NETWORKS (CIRCUITS);

EID: 41549156614     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2007.911339     Document Type: Conference Paper

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