Optimization of robust asynchronous circuits by local input completeness relaxation

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2007, Pages 622-627

  Jeong, Cheoljoo ^a   Nowick, Steven M ^a  

^a Department of Earth and Environmental Sciences   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; CANNING; COMPUTER AIDED DESIGN; DELAY CIRCUITS; DIGITAL INTEGRATED CIRCUITS; HEURISTIC PROGRAMMING; INDUSTRIAL ENGINEERING; MECHANIZATION; NETWORKS (CIRCUITS); OPTIMIZATION; PROCESS DESIGN; PROCESS ENGINEERING; TIME MEASUREMENT;

ASYNCHRONOUS CIRCUITS; CRITICAL PATHS; DEEP SUB-MICRON (DSM); DESIGN AUTOMATION CONFERENCE (DAC); LOCAL RELAXATION; OPTIMIZATION ALGORITHMS; PROCESS ,TEMPERATURE AND VOLTAGE (PVD); SOUTH PACIFIC;

TIMING CIRCUITS;

EID: 41549086550     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2007.358055     Document Type: Conference Paper

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