Checking delay-insensitivity: 104 gates and beyond

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2002, Pages 149-157

  Kondratyev, Alex ^a   Neukom, Lawrence ^b   Roig, Oriol ^c   Taubin, Alexander ^d   Fant, Karl ^e  

^a Cadence Berkeley Lab   (United States)

^b Verific Design Automation   (United States)

^c Cadence Technology   (United States)

^d BOSTON UNIVERSITY   (United States)

^e Theseus Research   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT BEHAVIORS; DELAY INSENSITIVE CIRCUITS; DELAY-INSENSITIVITY; DESIGN TECHNIQUE; GATE DELAYS; NEW APPROACHES; SATISFIABILITY SOLVERS; VERIFICATION TASK; WIRE DELAYS;

DELAY CIRCUITS;

EID: 77957932591     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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