Average-case optimized transistor-level technology mapping of extended burst-mode circuits

Proceedings - 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems

Volumn 1998-March, Issue , 1998, Pages 70-79

  James, Kevin W ^a   Yun, Kenneth Y ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; TIMING CIRCUITS;

ASYNCHRONOUS CONTROLLERS; AUTOMATED METHODS; AVERAGE CASE; ELMORE DELAY; NEAR-OPTIMAL; NEAR-OPTIMAL PERFORMANCE; TECHNOLOGY MAPPING; TRANSISTOR LEVEL;

DELAY CIRCUITS;

EID: 77957942439     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.1998.666495     Document Type: Conference Paper

References (10)

1. [I] P. A. Beerel, K. Y. Yun, W. C. Chou. A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burstmode circuits. In Proc. European Design Automation Conference (EURO-DAC), September 1996.
2. P. A. Beerel, K. Y. Yun, W. C. Chou. Optimizing average-case delay in technology mapping of burstmode circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996.
3. S. M. Burns. General condition for the decomposition of state holding elements. In Proc. lnrernational Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996.
4. A. Davis, B. Coates, K. Stevens. The Post Office experience: Designing a large asynchronous chip. In Proc. Hawaii International ConJ System Sciences, volume I, pages 4 0 9 4 18. IEEE Computer Society Press, January 1993.
5. S. M. Nowick and D. L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. IEEE Transactions on Computer-Aided Design, 14(8):98-997, August 1995.
6. S. H. Unger. AsynchronousSequenrialSwitching Circuits. Wiley-Interscience, John Wiley & Sons, Inc., New York, 1969.
7. N. Weste and K. Eshraghian. Principles of CMOS VU1 Design (Second Edition). Addison-Wesley, 1992.
8. K. Y. Yun. Synthesis ofAsynchronous Controllersfor Heterogeneous Systems. PhD thesis, Stanford University, August 1994.
9. K. Y. Yun. Automatic synthesis of extended burstmode circuits using generalized C-elements. In Proc. European Design Automation Conference (EURODAC), pages 290-295, September 1996.
10. K. Y. Yun, P. A. Beerel, V. Vakilotojar, A. E. Dooply, J. Arceo. The design and verification of a highperformance low-control-overhead asynchronous differential equation solver. In Proc. Intemational Symposium on Advanced Research in Asynchronous Circuits und Systems, pages 140-153, April 1997.