Coping with the variability of combinational logic delays

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2004, Pages 505-508

  Cortadella, J ^a   Kondratye, A ^b   Lavagno, L ^c   Sotiriou, C ^d  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b CADENCE DESIGN SYSTEMS   (United States)

^c POLITECNICO DI TORINO   (Italy)

^d INSTITUTE OF COMPUTER SCIENCE   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN NETWORKS; CIRCUIT DESIGN; LOGIC DELAYS; SIGNAL INTEGRITY;

BENCHMARKING; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER NETWORKS; COMPUTER SIMULATION; DATA COMMUNICATION SYSTEMS; DIGITAL CIRCUITS; ENCODING (SYMBOLS);

LOGIC PROGRAMMING;

EID: 17644388873     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2004.1347969     Document Type: Conference Paper

References (16)

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