Technology mapping for area optimized quasi delay insensitive circuits

IFIP International Federation for Information Processing

Volumn 240, Issue , 2007, Pages 55-69

  Folco, Bertrand ^a   Brégier, Vivian ^a   Fesquet, Laurent ^a   Renaudin, Marc ^a  

^a TIMA LABORATORY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; CONFORMAL MAPPING; VLSI CIRCUITS; WIRE; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER PROGRAMMING LANGUAGES; DELAY CIRCUITS; HIGH LEVEL LANGUAGES; HIGH LEVEL SYNTHESIS; MANY VALUED LOGICS; MAPPING; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS;

AREA OPTIMIZED; ASYNCHRONOUS CIRCUITS; HIGH ROBUSTNESS; MULTI-VALUED DECISION DIAGRAMS; QUASI-DELAY-INSENSITIVE CIRCUITS; STANDARD CELL; TECHNOLOGY MAPPING; TECHNOLOGY MAPPING ALGORITHMS;

DELAY CIRCUITS; ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 34548715371     PISSN: 15715736     EISSN: None     Source Type: Book Series    
DOI: 10.1007/978-0-387-73661-7_5     Document Type: Conference Paper

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