Optimization of NULL convention self-timed circuits

Integration, the VLSI Journal

Volumn 37, Issue 3, 2004, Pages 135-165

  Smith, Scott C ^a   DeMara, Ronald F ^b   Yuan, J S ^b   Ferguson, David ^c   Lamb, David ^c  

^a Missouri University of Science and Technology   (United States)

^b UNIVERSITY OF CENTRAL FLORIDA   (United States)

^c Theseus Logic Inc   (United States)

Author keywords

Asynchronous logic design; Dual rail encoding; Full adder; NULL convention logic (NCL); Quad rail encoding; Self timed circuits; Threshold gates; Up counter

Indexed keywords

BOOLEAN ALGEBRA; LOGIC GATES; MATHEMATICAL MODELS; MICROCONTROLLERS; OPTIMIZATION; TRANSISTORS;

ASYNCHRONOUS LOGIC DESIGN; DUAL-RAIL ENCODING; QUAD-RAIL ENCODING; SELF-TIMED CIRCUITS;

LOGIC CIRCUITS;

EID: 3342915035     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2003.12.004     Document Type: Article

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