General conditions for the decomposition of state holding elements

Proceedings - 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC 1996

Volumn , Issue , 1996, Pages 48-57

  Burns, S M ^a  

^a UNIVERSITY OF WASHINGTON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC;

ARBITRARY STATE; ASYNCHRONOUS CIRCUITS; HIGH FAN-IN; INTERNAL SIGNALS; PARAMETERIZED; SPEED INDEPENDENT;

DECOMPOSITION;

EID: 84899571087     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.1996.494437     Document Type: Conference Paper

References (12)

1. P. Beerel. CAD tools for the synthesis, verification, and testability of robust asynchronous circuits. Ph.D. thesis, Stanford University, 1994.
2. P.A. Beerel, J.R. Burch, and T.H-Y. Meng. Sufficient conditions for correct gate-level speed-independent circuits. In Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 33-43. IEEE Computer Society Press, 1994.
3. F. M. Brown. Boolean reasoning: the logic of Boolean equations. Kluwer Academic Publishers, Boston, 1990.
4. J. R. Burch, E. M. Clarke, D. E. Long, K. L. McMillan, and D. L. Dill. Symbolic model checking for sequential circuit verification. IEEE Transactions on Computer-Aided Design of Integrated Circuits, 13(4), April 1994.
5. D. Cronquist and S. M. Burns. Synthesis and analysis of a delay-insensitive folded FIFO. ftp://ftp.cs.washington.edu/pub/lis/burns/tau95.ps.gz, November 1995.
6. S. Hauck, G. Borriello, C. Ebeling, and S. Burns. An FPGA for implementing asynchronous circuits. IEEE Design & Test of Computers, ll(3):60-69, 1994.
7. B. Lin, C. Ykman-Couvreur, and P. Vanbekbergen. A general state graph transformation framework for asynchronous synthesis. In Proc. EURO-DAC '94 with EURO-VHDL '94, pages 448-53, September 1994.
8. A. J. Martin, Programming in VLSI: Prom communicating processes to delay-insensitive circuits. In C.A.R. Hoare, editor, UT Year of Programming Institute on Concurrent Programming. Addison-Wesley, Reading, MA, 1990.
9. A.J. Martin. The limitation to delay-insensitivity in asynchronous circuits. In William J. Dally, editor, Advanced Research in VLSI: Proceedings of the Sixth MIT Conference, pages 263-278, Cambridge, MA, 1990. MIT Press.
10. P. S. K. Siegel. Automatic technology mapping for asynchronous designs. Ph.D. thesis, Stanford University, 1995.
11. R. T. Stanion. Boolean algorithms for combinational synthesis and test generation. Ph.D. thesis, Yale University, 1994.
12. P. Vanbekbergen, B. Lin, G. Goossens, and H. De Man. A generalized state assignment theory for transformations on signal transitions graphs. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 112-117, November 1992.