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Volumn , Issue , 2006, Pages 158-163

Cost-aware synthesis of asynchronous circuits based on partial acknowledgement

Author keywords

[No Author keywords available]

Indexed keywords

ACKNOWLEDGEMENT (ACK); ASYNCHRONOUS CIRCUITS; COMPUTER-AIDED DESIGN; DESIGN FLOWS; INTERNATIONAL CONFERENCES; NET LIST; REDUCTION IN AREA (RA); SOFTWARE TOOLS; SYNTHESIS (OF CHIRAL IONIC LIQUIDS); TIMING VERIFICATION;

EID: 38049063843     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320080     Document Type: Conference Paper
Times cited : (37)

References (21)
  • 1
    • 0026882866 scopus 로고
    • Beware the isochronic fork
    • June
    • K. v. Berkel. Beware the isochronic fork. Integration, the VLSI journal, 13(2):103-128, June 1992.
    • (1992) Integration, the VLSI journal , vol.13 , Issue.2 , pp. 103-128
    • Berkel, K.V.1
  • 6
    • 0036646467 scopus 로고    scopus 로고
    • Design of asynchronous circuits using synchronous CAD tools
    • A. Kondratyev and K. Lwin. Design of asynchronous circuits using synchronous CAD tools. IEEE Design & Test of Computers, 19(4):107-117, 2002.
    • (2002) IEEE Design & Test of Computers , vol.19 , Issue.4 , pp. 107-117
    • Kondratyev, A.1    Lwin, K.2
  • 9
    • 0002927123 scopus 로고
    • Programming in VLSI: From communicating processes to delay-insensitive circuits
    • C. A. R. Hoare, editor, Developments in Concurrency and Communication, Addison-Wesley
    • A. J. Martin. Programming in VLSI: From communicating processes to delay-insensitive circuits. In C. A. R. Hoare, editor, Developments in Concurrency and Communication, UT Year of Programming Series, pages 1-64. Addison-Wesley, 1990.
    • (1990) UT Year of Programming Series , pp. 1-64
    • Martin, A.J.1
  • 10
    • 34249834238 scopus 로고
    • Asynchronous datapaths and the design of an asynchronous adder
    • July
    • A. J. Martin. Asynchronous datapaths and the design of an asynchronous adder. Formal Methods in System Design, 1(1):119-137, July 1992.
    • (1992) Formal Methods in System Design , vol.1 , Issue.1 , pp. 119-137
    • Martin, A.J.1
  • 13
    • 0028697961 scopus 로고
    • Evaluation of function blocks for asynchronous design
    • IEEE Computer Society Press, Sept
    • C. D. Nielsen. Evaluation of function blocks for asynchronous design. In Proc. European Design Automation Conference (EURO-DAC), pages 454-459. IEEE Computer Society Press, Sept. 1994.
    • (1994) Proc. European Design Automation Conference (EURO-DAC) , pp. 454-459
    • Nielsen, C.D.1
  • 16
    • 0001951703 scopus 로고
    • System timing
    • C. A. Mead and L. A. Conway, editors, chapter 7. Addison-Wesley
    • C. L. Seitz. System timing. In C. A. Mead and L. A. Conway, editors, Introduction to VLSI Systems, chapter 7. Addison-Wesley, 1980.
    • (1980) Introduction to VLSI Systems
    • Seitz, C.L.1
  • 20
    • 0027677633 scopus 로고
    • Delay-insensitive multi-ring structures
    • Oct
    • J. Sparsø and J. Staunstrup. Delay-insensitive multi-ring structures. Integration, the VLSI journal, 15(3):313-340, Oct. 1993.
    • (1993) Integration, the VLSI journal , vol.15 , Issue.3 , pp. 313-340
    • Sparsø, J.1    Staunstrup, J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.