메뉴 건너뛰기




Volumn 31, Issue 1, 2008, Pages 4-13

Integrating through-wafer interconnects with active devices and circuits

Author keywords

Integrated circuit (IC) packaging; Interconnects

Indexed keywords

ELECTRONICS PACKAGING; MASKS; MICROELECTRONICS; MICROPROCESSOR CHIPS;

EID: 40549139509     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2007.906235     Document Type: Article
Times cited : (17)

References (29)
  • 1
    • 0036134737 scopus 로고    scopus 로고
    • A vertical leap for microchips
    • T. H. Lee, "A vertical leap for microchips," Sci. Amer., vol. 286, p. 52, 2002.
    • (2002) Sci. Amer , vol.286 , pp. 52
    • Lee, T.H.1
  • 2
    • 12944317214 scopus 로고    scopus 로고
    • High density packaging: The next interconnect challenge
    • J. Baliga, "High density packaging: The next interconnect challenge," Semicond. Int., vol. 23, p. 91, 2000.
    • (2000) Semicond. Int , vol.23 , pp. 91
    • Baliga, J.1
  • 3
    • 33749066552 scopus 로고    scopus 로고
    • 3DICs solve the interconnect paradox
    • J. Baliga, "3DICs solve the interconnect paradox," Semicond. Int. vol. 28, no. 6, p. 7, 2005.
    • (2005) Semicond. Int , vol.28 , Issue.6 , pp. 7
    • Baliga, J.1
  • 5
    • 0037738328 scopus 로고    scopus 로고
    • Advancements instacked chip scale packaging provides system in a package functionality for wireless and handheld applications
    • M. Kada and L. Smith, "Advancements instacked chip scale packaging provides system in a package functionality for wireless and handheld applications," in Proc. 5th Pan Pacific Microelectron. Symp., 2000, pp. 246-251.
    • (2000) Proc. 5th Pan Pacific Microelectron. Symp , pp. 246-251
    • Kada, M.1    Smith, L.2
  • 6
    • 4444306456 scopus 로고    scopus 로고
    • Stacked-die packaging: Technology toolbox
    • M. Karnezos, "Stacked-die packaging: Technology toolbox," Adv. Packag., vol. 13, pp. 41-4, 2004.
    • (2004) Adv. Packag , vol.13 , pp. 41-44
    • Karnezos, M.1
  • 7
    • 0031704062 scopus 로고    scopus 로고
    • Through-wafer electrical interconnects by sidewall photolithographic patterning
    • St. Paul, MN
    • C. Liu, "Through-wafer electrical interconnects by sidewall photolithographic patterning," in IEEE Instrum. Measurement Technol. Conf., St. Paul, MN, 1998, pp. 1402-1405.
    • (1998) IEEE Instrum. Measurement Technol. Conf , pp. 1402-1405
    • Liu, C.1
  • 9
    • 0001081074 scopus 로고    scopus 로고
    • Ultra-low resistance, through-wafer via technology and its applications in three dimensional structures on silicon
    • H. T. Soh, C. P. Yue, A. McCarthy, C. Ryu, T. H. Lee, S. S. Wong, and C. F. Quate, "Ultra-low resistance, through-wafer via technology and its applications in three dimensional structures on silicon," Jpn. J. Appl. Phys., vol. 38, pp. 2393-2396, 1999.
    • (1999) Jpn. J. Appl. Phys , vol.38 , pp. 2393-2396
    • Soh, H.T.1    Yue, C.P.2    McCarthy, A.3    Ryu, C.4    Lee, T.H.5    Wong, S.S.6    Quate, C.F.7
  • 11
    • 84961696384 scopus 로고    scopus 로고
    • Opportunities for reduced power dissipation using three-dimensional integration
    • J. W. Joyner and J. D. Meindl, "Opportunities for reduced power dissipation using three-dimensional integration," in 2002 IEEE Interconnect Technol. Conf., 2002, pp. 148-150.
    • (2002) 2002 IEEE Interconnect Technol. Conf , pp. 148-150
    • Joyner, J.W.1    Meindl, J.D.2
  • 13
    • 40049092242 scopus 로고    scopus 로고
    • Characterization of a two-dimensional cantilever array with through-wafer electrical interconnects
    • E. M. Chow, G. g. Yaralioglu, C. F. Quate, and T. W. Kenny, "Characterization of a two-dimensional cantilever array with through-wafer electrical interconnects," Appl. Phys. Lett., vol. 80, pp. 664-666, 2002.
    • (2002) Appl. Phys. Lett , vol.80 , pp. 664-666
    • Chow, E.M.1    Yaralioglu, G.G.2    Quate, C.F.3    Kenny, T.W.4
  • 14
    • 0242303135 scopus 로고    scopus 로고
    • High desnity, high aspect ratio through-wafer electrical interconnect vias for MEMS packaging
    • Aug
    • S. J. Ok, C. Kim, and D. F. Baldwin, "High desnity, high aspect ratio through-wafer electrical interconnect vias for MEMS packaging," IEEE Trans. Adv. Packag., vol. 26, no. 3, pp. 302-309, Aug. 2003.
    • (2003) IEEE Trans. Adv. Packag , vol.26 , Issue.3 , pp. 302-309
    • Ok, S.J.1    Kim, C.2    Baldwin, D.F.3
  • 17
    • 0036296681 scopus 로고    scopus 로고
    • Generic, direct-chip-attach MEMS packaging design with high density and aspect ratio through-wafer electrical interconnects
    • S. J. Ok, J. Neysmith, and D. F. Baldwin, "Generic, direct-chip-attach MEMS packaging design with high density and aspect ratio through-wafer electrical interconnects," in 2002 Electron. Compon. Technol. Conf. 2002, pp. 232-237.
    • (2002) 2002 Electron. Compon. Technol. Conf , pp. 232-237
    • Ok, S.J.1    Neysmith, J.2    Baldwin, D.F.3
  • 18
    • 4444224426 scopus 로고    scopus 로고
    • Microwave characterization of high aspect ratio through-wafer interconnect vias in silicon substrates
    • Jun
    • L. L. W. Leung and K. J. Chen, "Microwave characterization of high aspect ratio through-wafer interconnect vias in silicon substrates," IEEE Microwave Theory Tech. Soc. Digest, vol. 2, pp. 1197-1200, Jun. 2004.
    • (2004) IEEE Microwave Theory Tech. Soc. Digest , vol.2 , pp. 1197-1200
    • Leung, L.L.W.1    Chen, K.J.2
  • 19
    • 8144229690 scopus 로고    scopus 로고
    • A through-wafer interconnect in silicon for RFICs
    • Nov
    • J. H. Wu, J. Scholvin, and J. A. del Alamo, "A through-wafer interconnect in silicon for RFICs," IEEE Trans. Electron Devices, vol. 51, no. 11, pp. 1765-1771, Nov. 2004.
    • (2004) IEEE Trans. Electron Devices , vol.51 , Issue.11 , pp. 1765-1771
    • Wu, J.H.1    Scholvin, J.2    del Alamo, J.A.3
  • 23
    • 3042521416 scopus 로고    scopus 로고
    • Interaction effects of slurry chemistry on chemical mechancial planarization of electroplated copper
    • P. A. Miranda, J. A. Imonigie, and A. J. Moll, "Interaction effects of slurry chemistry on chemical mechancial planarization of electroplated copper," in IEEE Workshop Microelectron. Electron Devices, 2004, pp. 85-88.
    • (2004) IEEE Workshop Microelectron. Electron Devices , pp. 85-88
    • Miranda, P.A.1    Imonigie, J.A.2    Moll, A.J.3
  • 25
    • 40549090531 scopus 로고    scopus 로고
    • Rochester Institute of Technology Microelectronics Center, Online, Available
    • Rochester Institute of Technology Microelectronics Center 2006 [Online]. Available: http://smfl.microe.rit.edu/
    • (2006)
  • 26
    • 0021407489 scopus 로고
    • Dielectric breakdown of gate insulator due to reactive ion etching
    • T. Wadanabe and Y. Yoshida, "Dielectric breakdown of gate insulator due to reactive ion etching," Solid State Technol., pp. 263-266, 1984.
    • (1984) Solid State Technol , pp. 263-266
    • Wadanabe, T.1    Yoshida, Y.2
  • 27
    • 0346984355 scopus 로고
    • MOS gate insulator breakdown caused by exposure to plasma
    • Y. Kawamoto, "MOS gate insulator breakdown caused by exposure to plasma," in Dry Process Symp., Inst. Elect. Eng. Jpn., 1985, pp. 132-137.
    • (1985) Dry Process Symp., Inst. Elect. Eng. Jpn , pp. 132-137
    • Kawamoto, Y.1
  • 29
    • 0019656053 scopus 로고
    • Time-zero dielectric reliability test by a ramp method
    • A. Berman, "Time-zero dielectric reliability test by a ramp method," in IEEE Int. Rel. Phys. Symp, 1981, pp. 204-209.
    • (1981) IEEE Int. Rel. Phys. Symp , pp. 204-209
    • Berman, A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.