Wafer process and issue of through electrode in Si wafer using Cu damascene for three dimensional chip stacking

Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002

Volumn , Issue , 2002, Pages 75-77

  Hoshino, M ^a   Yonemura, H ^a   Tomisaka, M ^a   Fujii, T ^a   Sunohara, M ^a   Takahashi, K ^a  

^a ASSOCIATION OF SUPER ADVANCED ELECTRONICS TECHNOLOGIES ASET   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; ELECTRODES; SILICON WAFERS;

ELECTRONIC SYSTEMS; HIGH-DENSITY PACKAGING; PERFORMANCE BOTTLENECKS; PROCESS ISSUES; STACKING TECHNOLOGY; THREE DIMENSIONAL CHIP STACKING; THREEDIMENSIONAL (3-D); WAFER THINNING;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84961720975     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2002.1014892     Document Type: Conference Paper

References (11)

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