A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects

Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002

Volumn , Issue , 2002, Pages 78-80

  Lu, J Q ^a   Kwon, Y ^a   Rajagopalan, G ^a   Gupta, M ^a   McMahon, J ^a   Lee, K W ^a   Kraft, R P ^a   McDonald, J F ^a   Cale, T S ^a   Gutmann, R J ^a   Xu, B ^b   Eisenbraun, E ^b   Castracane, J ^b   Kaloyeros, A ^b  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^b STATE UNIVERSITY OF NEW YORK   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GRINDING (MACHINING); INTEGRATED CIRCUIT INTERCONNECTS; THREE DIMENSIONAL INTEGRATED CIRCUITS;

COPPER DAMASCENE; GRINDING AND POLISHING; IC TECHNOLOGY; THREEDIMENSIONAL (3-D); WAFER ALIGNMENT; WAFER INTERCONNECTS; WAFER SCALE; WAFER THINNING;

WAFER BONDING;

EID: 84961736622     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2002.1014893     Document Type: Conference Paper

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