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Volumn 28, Issue 6, 2005, Pages

Three-Dimensional ICs Solve the Interconnect Paradox
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EID: 33749066552     PISSN: 01633767     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article
Times cited : (4)

References (15)
  • 2
    • 33749054084 scopus 로고    scopus 로고
    • Interconnection-oriented computer architecture
    • IEEE
    • W. Dally, "Interconnection-Oriented Computer Architecture," Proc. of the 1999 IITC, IEEE, 1999, p.15.
    • (1999) Proc. of the 1999 IITC , pp. 15
    • Dally, W.1
  • 6
    • 85001141006 scopus 로고    scopus 로고
    • Thermal analysis of three-Dimensional (3-D) Integrated Circuits (ICs)
    • IEEE
    • A. Rahman and R. Reif, "Thermal Analysis of Three-Dimensional (3-D) Integrated Circuits (ICs)," Proc. of the 2001 IITC, IEEE, 2001, p. 157.
    • (2001) Proc. of the 2001 IITC , pp. 157
    • Rahman, A.1    Reif, R.2
  • 7
    • 84961696384 scopus 로고    scopus 로고
    • Opportunities for reduced power dissipation using three-dimensional integration
    • IEEE
    • J. Joyner and J. Meindl, "Opportunities for Reduced Power Dissipation Using Three-Dimensional Integration," Proc. of the 2002 IITC, IEEE, 2002, p. 148.
    • (2002) Proc. of the 2002 IITC , pp. 148
    • Joyner, J.1    Meindl, J.2
  • 8
    • 1542607353 scopus 로고    scopus 로고
    • Chips go vertical
    • March
    • J. Baliga, "Chips Go Vertical," IEEE Spectrum, March 2004, p. 43.
    • (2004) IEEE Spectrum , pp. 43
    • Baliga, J.1
  • 9
    • 3042803978 scopus 로고    scopus 로고
    • Mixing signals with 3-D integration
    • November
    • R. Markunas, "Mixing Signals With 3-D Integration," Semiconductor International, November 2002, p. 63.
    • (2002) Semiconductor International , pp. 63
    • Markunas, R.1
  • 10
    • 6744237810 scopus 로고    scopus 로고
    • Packaging provides viable alternatives to SOC
    • July
    • J. Baliga, "Packaging Provides Viable Alternatives to SOC," Semiconductor International, July 2000, p. 169.
    • (2000) Semiconductor International , pp. 169
    • Baliga, J.1
  • 11
    • 84961724195 scopus 로고    scopus 로고
    • A methodology for the interconnect performance evaluation of 2-D and 3-D processors with memory
    • IEEE
    • G. Chandra, P. Kapur and K. Saraswat, "A Methodology for the Interconnect Performance Evaluation of 2-D and 3-D Processors With Memory, " Proc. of the 2002 IITC, IEEE, 2002, p. 164.
    • (2002) Proc. of the 2002 IITC , pp. 164
    • Chandra, G.1    Kapur, P.2    Saraswat, K.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.