Microwave characterization of high aspect ratio through-wafer interconnect vias in silicon substrates

IEEE MTT-S International Microwave Symposium Digest

Volumn 2, Issue , 2004, Pages 1197-1200

  Leung, Lydia Lap Wai ^a   Chen, Kevin J ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

MEMS; RF packaging; Silicon substrate; Through wafer interconnects; Via holes

Indexed keywords

ASPECT RATIO; ETCHING; FREQUENCIES; MICROWAVES; RESONANCE; SILICON WAFERS; SUBSTRATES; TUNING;

PATCH ANTENNAS; THROUGH-WAFER INTERCONNECTS; VOIDS; WAFER DICING;

ELECTRONICS PACKAGING;

EID: 4444224426     PISSN: 0149645X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. S. J. Ok, C. Kim, and Daniel Baldwin, "High density, high aspect-ratio through-wafer electrical interconnects vias for MEMS packaging", IEEE Trans. On Advanced Packaging, vol. 26, 2003, pp. 302-309.
2. C. H. Cheng, A. S. Etgun and B. T. Khuri-Yakub, "Electrical Through-Wafer Interconnects with Sub-PicoFarad Parasitic Capapcitance", Microelectromechanical Systems Conference, 2001, pp. 18-21.
3. E. M. Chow, V. C. Chandrasekaran, A. Partridge, T. Nishida, M. Sheplak, C. F. Quate and T. W. Kenny, "Process Compatible Polysilicon-based Electrical Through-wafer Interconnects in Silicon Substrate", Journal of Microelectromechanical systems, vol. 11, No. 6, Dec. 2002, pp. 631-640.
4. N. T. Nguyen, E. Boellaard, N. P. Pham, V. G. Kutchokov, G. Craciun and P. M. Sarro, "Through-wafer copper electroplating for three-dimensional interconnects", Journal of Micromechanics and Microengineering 2002, vol. 12, pp. 395 -399.
5. Joyce H. Wu, Jesus A. del Alamo, and Keith A. Jenkins, "A High Aspect-Ratio Silicon Substrate-Via Technology and Applications: Through-Wafer Interconnects for Power and Ground and Faraday Cages for SOC Isolation", International Electronic Devices Meeting, 2000, pp. 477-480.
6. R. Uscola and M. Tutt, "Determining the Inductance of a Through-Substrate Via Using Mulitple On-wafer test approaches", Proc. IEEE Int. Conference on Microelectronic Test structures, vol. 14, March 2001, pp. 147-151.