Error moderation in low-cost machine-learning-B ased analog/RF testing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 2, 2008, Pages 339-351

  Stratigopoulos, Haralampos G ^a,b   Makris, Yiorgos ^a,c  

^a IEEE

^b CNRS   (France)

^c Yale University   (United States)

Author keywords

Alternate testing; Analog circuits; Circuit testing; Machine learning; RF circuits

Indexed keywords

ANALOG CIRCUITS; COST BENEFIT ANALYSIS; ERROR CORRECTION; NEURAL NETWORKS; SIGNAL RECEIVERS; STANDARDS;

ALTERNATE TESTING; CIRCUIT TESTING; RF CIRCUITS; TRAINING ALGORITHMS;

LEARNING SYSTEMS;

EID: 38649126532     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2007.907232     Document Type: Article

References (42)

1. D. Gizopoulos, Ed., Advances in Electronic Testing, ser. Frontiers in Electronic Testing. New York: Springer-Verlag, 2006.
2. C. Y. Pan and K. T. Cheng, "Pseudorandom testing for mixed-signal circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 16, no. 10, pp. 1173-1185, Oct. 1997.
3. C. Y. Pan and K. T. Cheng, "Test generation for linear time-invariant analog circuits," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 5, pp. 554-564, May 1999.
4. W. M. Lindermeir, H. E. Graeb, and K. J. Antreich, "Analog testing by characteristic observation inference," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 9, pp. 1353-1368, Sep. 1999.
5. P. N. Variyam and A. Chatterjee, "Specification-driven test generation for analog circuits," IEEE Trans. Comput. -Aided Design Integr. Circuits Syst., vol. 19, no. 10, pp. 1189-1201, Oct. 2000.
6. V. Stopjakova, P. Malosek, D. Micusik, M. Matej, and M. Margala, "Classification of defective analog integrated circuits using artificial neural networks," I. Electron. Test.: Theory Appl., vol. 20, no. 1, pp. 25-37, Feb. 2004.
7. V. Stopjakova, P. Malosek, M. Matej, V. Nagy, and M. Margala, "Defect detection in analog and mixed circuits by neural networks using wavelet analysis," IEEE Trans. Rel., vol. 54, no. 3, pp. 441-448, Sep. 2005.
8. H.-G. D. Stratigopoulos and Y. Makris, "Nonlinear decision boundaries for testing analog circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 1.1, pp. 1760-1773, Nov. 2005.
9. P. N. Variyam, S. Cherubal, and A. Chatterjee, "Prediction of analog performance parameters using fast transient testing," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 21, no. 3, pp. 349-361, Mar. 2002.
10. R. Voorakaranam, S. Cherubal, and A. Chatterjee, "A signature test framework for rapid production testing of RF circuits," in Proc. Des., Autom. Test Eur., 2002, pp. 186-191.
11. R. Voorakaranam, R. Newby, S. Cherubal, B. Cometta, T. Kuehl, D. Majernik, and A. Chatterjee, "Production deployment of a fast transient testing methodology for analog circuits: Case study and results," in Proc. IEEE Int. Test Conf, 2003, pp. 1174-1181.
12. S.S. Akbay and A. Chatterjee, "Feature extraction based built-in alternate test of RF components using a noise reference," in Proc. IEEE VLSI Test Symp., 2004, pp. 273-278.
13. S. Bhattacharya and A. Chatterjee, "Use of embedded sensors for built-in-test of RF circuits," in Proc. IEEE Int. Test Conf., 2004, pp. 801-809.
14. A. Raghunathan, J. H. Chun, J. A. Abraham, and A. Chatterjee, "Quasioscillation based test for improved prediction of analog performance parameters," in Proc. IEEE Int. Test Conf., 2004, pp. 252-261.
15. S. S. Akbay, A. Halder, A. Chatterjee, and D. Keezer, "Low-cost test of embedded RF/analog/mixed-signal circuits in SOPs," IEEE Trans. Adv. Packag., vol. 27, no. 2, pp. 352-363, May 2004.
16. S. S. Akbay and A. Chatterjee, "Built-in test of RF components using mapped feature extraction sensors," in Proc. IEEE VLSI Test Symp., 2005, pp. 243-248.
17. G. Srinivasan, S. Bhattacharya, S. Cherubal, and A. Chatterjee, "Fast specification test of TDMA power amplifiers using transient current measurements," Proc. Inst. Electr. Eng.-Comput. Digit. Tech., vol. 152, no. 5, pp. 632-642, Sep. 2005.
18. G. Srinivasan, A. Chatterjee, and F. Taenzler, "Alternate loop-back diagnostic tests for water-level diagnosis of modern wireless transceivers using spectral signatures," in Proc. IEEE VLSI Test Symp., 2006, pp. 222-227.
19. S. S. Akbay, J. L. Torres, J. M. Rumer, A. Chatterjee, and J. Amtsfleld, "Alternate test of RF front ends with IP constraints: Frequency domain test generation and validation," in Proc. IEEE Int. Test Conf., 2006, pp. 4.4.1-4.4.10.
20. S. Ellouz, P. Gamand, C. Kelma, B. Vandewiele, and B. Allard, "Combining internal probing with artificial neural networks for optimal RFIC testing," in Proc. IEEE Int. Test Conf., 2006, pp. 4.3.1-4.3.9.
21. P. Collins, S. Yu, K. R. Eckersall, B. W. Jervis, I. M. Bell, and G. E. Taylor, "Application of Kohonen and supervised forced organization maps to fault diagnosis in CMOS opamps," Electron. Lett., vol. 30, no. 22, pp. 1846-1847, Oct. 1994.
22. S. Yu, B. W. Jervis, K. R. Eckersall, I. M. Bell, A. G. Hall, and G. E. Taylor, "Neural network approach to fault diagnosis in CMOS opamps with gate oxide short faults," Electron. Lett., vol. 30, no. 9, pp. 695-696, Apr. 1994.
23. S. S. Somayajula, E. Sanchez-Sinencio, and J. P. de Gyvez, "Analog fault diagnosis based on ramping power supply current signature clusters," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 43, no. 10, pp. 703-712, Oct. 1996.
24. R. Spina and S. Upadhyaya, "Linear circuit fault diagnosis using neuromorphic analyzers," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 44, no. 3, pp. 188-196, Mar. 1997.
25. Y. Maidon, B. W Jervis, N. Dutton, and S. Lesage, "Diagnosis of multifaults in analogue circuits using multilayer perceptrons," Proc. Inst. Electr. Eng.-Circuits Devices Syst., vol. 144, no. 3, pp. 149-154, Jun. 1997.
26. Z. R. Yang, M. Zwolinski, C. D. Chalk, and A. C. Williams, "Applying a robust heteroscedastic probabilistic neural network to analog fault detection and classification," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 19, no. 1, pp. 142-151, Jan. 2000.
27. J. H. Friedman, "Multivariate adaptive regression splines," Ann. Stat., vol. 19, no. 1, pp. 1-67, 1991.
28. C. M. Bishop, Neural Networks for Pattern Recognition. London, U.K.: Oxford Univ. Press, 1995.
29. S. Biswas, P. Li, R. D. S. Blanton, and L. Pileggi, "Specification test compaction for analog circuits and MEMS," in Proc. Des., Autom. Test Eur., 2005, pp. 164-169.
30. V. Honavar and L. Uhr, "Generative learning structures and processes for generalized connectionist networks," Inf. Sci., vol. 70, no. 1/2, pp. 75-108, 1993.
31. R. Parekh, J. Yang, and V. Honavar, "Constructive neural-network learning algorithms for pattern classification," IEEE Trans. Neural Netw., vol. 11, no. 2, pp. 436-451, Mar. 2000.
32. M. Frean, "A 'thermal' perceptron learning rule," Neural Comput., vol. 4, no. 6, pp. 946-957, Nov. 1992.
33. S. I. Gallant, "Perceptron-based learning algorithms," IEEE Trans. Neural Netw., vol. 1, no. 2, pp. 179-191, Jun. 1990.
34. N. Burgess, "A constructive algorithm, that converges for real-valued input patterns," Int. I. Neural Syst., vol. 5, no. 1, pp. 59-66, 1994.
35. D. Brown, J. Ferrado, R. Wolf, J. Li, and J. Bhagat, "RF testing on a mixed-signal tester," in Proc. IEEE Int. Test Conf, 2004, pp. 793-800.
36. J. P. de Gyvez, G. Gronthoud, and R. Amine, "VDD ramp testing for RF circuits," in Proc. IEEE Int. Test Conf, 2003, pp. 651-658.
37. M. Kudo and J. Sklansky, "Comparison of algorithms that select features for pattern classifiers," Pattern Recognit, vol. 33, no. 1, pp. 25-4.1, 2000.
38. W. Siedlecki and J. Sklansky, "A note on genetic algorithms for large-scale feature selection," Pattern Recognit. Lett., vol. 10, no. 5, pp. 335-347, Nov. 1989.
39. D.E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning. Reading, MA: Addison-Wesley, 1989.
40. K. Deb, A. Pratap, A. Agarwal, and T. Meyarivan, "A fast and elitist multiobjective genetic algorithm: NSGA-II," IEEE Trans. Evol Comput., vol. 6, no. 2, pp. 182-197, Apr. 2002.
41. R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Processing. Hoboken, NJ: Wiley, 1986.
42. P. Horowitz and W. Hill, The Art of Electronics. Cambridge, U.K.: Cambridge Univ. Press, 1989.