Specification test compaction for analog circuits and MEMS

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn I, Issue , 2005, Pages 164-169

  Biswas, Sounil ^a   Li, Peng ^b   Blanton, R D ^a   Pileggi, Larry T ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITS; DEFECT ESCAPE; NON-DIGITAL INTEGRATED SYSTEM; REDUNDANT TESTS;

ACCELEROMETERS; COMPACTION; COSTS; MICROELECTROMECHANICAL DEVICES; OPERATIONAL AMPLIFIERS; STATISTICAL METHODS;

INTEGRATED CIRCUITS;

EID: 33646901319     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.277     Document Type: Conference Paper

References (15)

1. B. Vinnakota, "Automatic Test Generation Algorithm" Analog and Mixed-Signal Test, Prentice Hall Publishers, Upper Saddle River, NJ, Chap. 4, pp. 93-110, 1998.
2. M. Sachdev, "Defect Oriented Analog Testing: Strengths and Weaknesses", Proc. of the European Solid-State Circuits Conference, pp. 224-227, Sept. 1994.
3. M. Negreiros, L. Carro and A. A. Susin, "Ultimate Low Cost Analog BIST," Proc. of Design Automation Conf., pp. 570-573, June 2003.
4. N. Deb and R. D. Blanton, "Multi-Modal Built-in Self-Test for Symmetric Microsystems," Proc. of VLSI Test Symp., pp. 139-147, Apr. 2004.
5. M. Hafed and G. W. Roberts, "High Frequency Integrated Test And Measurement Using a Mixed-Signal Test Core", IEEE Trans. On Instrumentation and Measurement, Vol. 52, No. 6, pp. 1780-1786, Dec. 2003.
6. A. Haldar, S. Bhattacharya and A. Chatterjee, "Automatic Multitone Alternate Test Generation for RF Circuits Using Behavioral Models", Proc. of the Intl. Test Conf., pp. 665-673, Oct. 2003.
7. V. N. Vapnik, "Statistical Learning Theory," Wiley-Interscience Publishers, New York, NY, 1998.
8. A. J. Smola and B. Schölkopf, "A Tutorial on Support Vector Regression," NeuroCOLT Technical Report (downloadable from http://kernel-machines.org), Royal Holloway College, University of London, UK, 1998.
9. L. T. Pillage, A. R. Rohrer and C. Vishweswariah, "Electronic Circuit & System Simulation Methods," McGraw-Hill Publishers, New York, NY, 1994.
10. Li-C. Wang, T. M. Mak, K. T. Cheng and M. S. Abadir, "On Path-Based Learning and Its Applications in Delay Test and Diagnosis," Proc. of Design Automation Conf., pp. 492-497, June 2004.
11. Cadence Inc., Virtuoso Spectre Circuit Simulator San Jose, CA, 2003.
12. G. Wong, G. Tse, Q. Jing, T. Mukherjee and G. Fedder, "Accuracy and Composability in NODAS", Proc. of Intl. Workshop on Behavioral Modeling and Simulation, pp. 82-87, Oct. 2003.
13. I. Tsochantaridis, T. Hofmann, T. Joachims and Y. Altun, "Support Vector Machine Learning for Interdependent and Structured Output Spaces," Proc. of Intl. Conf. on Machine Learning, 2004.
14. T. Maudie, T. Miller, R. Nielsen, D. Wallace, T. Ruehs and D. Zehrbach, "Challenges of MEMS Device Characterization in Engineering Development and Final Manufacturing," Proc. of Systems Readiness Technology Conf., pp. 164-170, Aug. 1998.
15. J. Wu, G. K. Fedder, and L. R. Carley, "A Low-Noise Low-Offset Chopper-Stabilized Capacitive-readout Amplifier for CMOS MEMS Accelerometers," Proc. of Intl. Solid State Circuits Conf., pp. 428-429, Feb. 2002.